PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES

• US 20160336926A1
• Filed: 07/25/2016
• Published: 11/17/2016
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Sharma, Santosh, Kinzer, Daniel M., Zhang, Ju Jason
• Granted Patent: US 10,135,275 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Claims

1. A level shift circuit, comprising:

a first inverter circuit comprising;

a first input terminal;

a first output terminal;

a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground; and

a first pull up device coupled between the drain of the first GaN-based transistor and a power supply,

wherein the first pull up device comprises a second GaN-based transistor having a gate driven with a voltage based on the voltage at the first output terminal, and wherein the first and second GaN-based transistors are of the same conductivity type.

2. The circuit of claim 1, wherein the power supply is a floating power supply.

3. The circuit of claim 1, wherein the gate of the second GaN-based transistor is coupled to an output of a buffer circuit, and wherein an input of the buffer circuit is coupled to the first output terminal.

4. The circuit of claim 3, wherein the buffer circuit is configured to generate a pulse in s to an input transition at the input of the buffer circuit,

5. The circuit of claim 1, further comprising a second pull up device coupled between the drain of the first GaN-based transistor and the power supply.

6. The circuit of claim 5, wherein the second pull up device conducts current passively.

7. The circuit of claim 5, further comprising a third pull up device coupled between the drain of the first GaN-based transistor and the power supply.

8. A level shift circuit, comprising:

a first inverter circuit comprising;

a first input terminal,

a first output terminal,

a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground, and

a first pull up device coupled between the drain of the first GaN-based transistor and a power supply; and

a second inverter circuit comprising;

a second input terminal,

a second output terminal,

a second GaN-based transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground, and a second pull up device coupled between the drain of the second GaN-based transistor and the power supply,

wherein the first pull up device comprises a third GaN-based transistor having a gate driven with a voltage based on the voltage at the second output terminal, and wherein the first, second, and third GaN-based transistors are of the same conductivity type.

9. The circuit of claim 8, wherein the gate of the third GaN-based transistor is coupled to an output of an inverter circuit, and wherein an input of the inverter circuit is coupled to the second output terminal.

10. The circuit of claim 9, wherein the inverter circuit comprises an inverter, and the input of the inverter is coupled to the second output terminal by one or more additional GaN-based transistors.

11. The circuit of claim 8, further comprising a second pull up device coupled between the drain of the first GaN-based transistor and the power supply.

12. The circuit of claim 11, wherein the second pull up device conducts current passively.

13. The circuit of claim 11, further comprising a third pull up device coupled between the drain of the first GaN-based transistor and the power supply.

14. A level shift circuit, comprising:

a first inverter circuit, comprising;

a first input terminal,

a first output terminal,

a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to an intermediate node, and a source coupled to a first reference voltage, and

a first pull up device coupled between the drain of the first GaN-based transistor and a first power supply; and

a buffer circuit, comprising;

a second GaN-based transistor having a gate coupled to the intermediate node, a drain coupled to a second power supply, and a source coupled to the first output terminal, and

a first pull down device coupled between the first output terminal and a second reference voltage.

15. The circuit of claim 14, wherein the first power supply is a floating power supply.

16. The circuit of claim 14, wherein the voltage of the first reference voltage supply is fixed.

17. The circuit of claim 14, wherein the voltage of the second reference voltage is configured to change in response to a signal at the first input terminal.

18. The circuit of claim 14, wherein the second power supply is a floating power supply.

19. The circuit of claim 14, wherein the first pull down device comprises a resistor.

20. The circuit of claim 14, wherein the gate of the second GaN-based transistor is coupled to the intermediate node by one or more additional GaN-based transistors.

21. The circuit of claim 20, wherein at least one of the one or more additional GaN-based transistors comprises a drain coupled to the first power supply.

22. The circuit of claim 20, wherein at least one of the one or more additional GaN-based transistors comprises a source coupled to a second pull down device, and wherein the second pull down device is coupled to the second reference voltage.