Semiconductor Structure with Stress-Reducing Buffer Structure

• US 20160343904A1
• Filed: 08/08/2016
• Published: 11/24/2016
• Est. Priority Date: 02/22/2014
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Dobrinsky, Alexander, Shur, Michael, Gaska, Remigijus
• Granted Patent: US 9,876,140 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

Claims

1. A semiconductor structure comprising:

a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa.

2. The structure of claim 1, further comprising a substrate immediately adjacent to the first side of the buffer layer.

3. The structure of claim 1, wherein the buffer structure further includes an intermediate layer located immediately adjacent to the second side of the buffer layer and a first semiconductor layer in the set of semiconductor layers, wherein the intermediate layer comprises a plurality of group III nitride semiconductor films.

4. The structure of claim 3, wherein the plurality of group III nitride semiconductor films form a superlattice.

5. The structure of claim 3, wherein a dislocation density at the second side of the buffer layer is less than or equal to approximately 1×

10⁹ dislocation cores per square centimeter.

6. The structure of claim 3, wherein the buffer structure is formed using a method comprising:

selecting a set of growth parameters for growing a buffer structure, wherein the set of growth parameters are configured to achieve a target effective lattice constant a for the buffer structure;

growing the buffer structure using the selected set of growth parameters, wherein the growing the buffer structure includes;

growing the buffer layer; and

growing the intermediate layer directly on the buffer layer, wherein the plurality of group III nitride semiconductor films have alternating tensile and compressive stresses, wherein the stresses are adjusted by varying a V/III ratio used during the growth of the plurality of group III nitride semiconductor films.

7. The structure of claim 3, wherein the set of semiconductor layers includes:

an n-type layer located immediately adjacent to the intermediate layer;

an active region located on a side of the n-type layer opposite the intermediate layer; and

a p-type layer located on a side of the active region opposite the n-type layer.

8. The structure of claim 7, wherein the active region is configured to emit ultraviolet radiation and has a threading dislocation density in a range of 1×

10³ to 5×

10⁹ threading dislocations per square centimeter.

9. The structure of claim 1, wherein the buffer layer is formed of aluminum nitride.

10. The structure of claim 1, wherein the plurality of islands includes a subset of islands of a first material, and a subset of islands of a second material distinct from the first material.

11. The structure of claim 10, wherein the first material and the second material are dissimilar nitride-based materials.

12. The structure of claim 1, wherein the plurality of islands have an average size in a range between approximately 1 nanometer and approximately 100 nanometers and an average spacing in a range between approximately 10 nanometers and approximately 200 nanometers.

13. The structure of claim 1, wherein the plurality of islands have an average height in a range of approximately 5 Angstroms to approximately 100 Angstroms.

14. The structure of claim 1, wherein the buffer layer further includes a second plurality of islands located directly on the single layer, wherein the second plurality of islands are coalesced into a second single layer on a side opposite the single layer.

15. An optoelectronic device comprising:

a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include;

an n-type layer located on the buffer structure;

an active region located on a side of the n-type layer opposite the buffer structure; and

a p-type layer located on a side of the active region opposite the n-type layer.

16. The device of claim 15, wherein the active region is configured to emit ultraviolet radiation.

17. The device of claim 15, wherein the buffer structure further includes an intermediate layer located immediately adjacent to the second side of the buffer layer and a first semiconductor layer in the set of semiconductor layers, wherein the intermediate layer comprises a plurality of group III nitride semiconductor films having alternating tensile and compressive stresses.

18. An optoelectronic device comprising:

a nitride-based buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

a set of group III nitride-based semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include;

a group III nitride-based n-type layer located on the buffer structure;

a group III nitride-based active region located on a side of the n-type layer opposite the buffer structure, wherein the active region is configured to emit ultraviolet radiation; and

a group III nitride-based p-type layer located on a side of the active region opposite the n-type layer.

19. The device of claim 18, wherein the buffer structure further includes an intermediate layer located immediately adjacent to the second side of the buffer layer and a first semiconductor layer in the set of semiconductor layers, wherein the intermediate layer comprises a plurality of group III nitride semiconductor films.

20. The device of claim 18, wherein the plurality of islands includes a subset of islands of a first material, and a subset of islands of a second material distinct from the first material, wherein the first material and the second material are dissimilar nitride-based materials.