SYSTEM ON CHIP INCLUDING CLOCK MANAGEMENT UNIT AND METHOD OF OPERATING THE SYSTEM ON CHIP

• US 20160350259A1
• Filed: 05/17/2016
• Published: 12/01/2016
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEON, Ho-yeon, Lee, Jae-gon, Choi, Youn-sik, Lee, Min-joung, Song, Jin-ook
• Granted Patent: US 10,430,372 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Claims

1. Clock management circuitry, comprising:

a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request; and

the first slave clock controller configured to control outputting a first clock signal based on the first command.

2. The clock management circuitry of claim 1, wherein the first master clock controller is configured to receive the first clock request from a processor.

3. The clock management circuitry of claim 1, wherein the first master clock controller is configured to receive the first clock request via a second channel from a hardware component.

5. The clock management circuitry of claim 1, wherein

the first slave clock controller is configured to send an acknowledgement to the first master clock controller via the first channel in response to outputting the first clock signal;

and

the first master clock controller is configured to output a second clock signal after receipt of the acknowledgement.

8. The clock management circuitry of claim 1, wherein the first slave clock controller is configured to receive a second clock request from a hardware component and is configured to control generating the first clock signal based on the first command and the second clock request.

10. The clock management circuitry of claim 8, wherein the first slave clock controller is configured to control generating the first clock signal based on an earlier received one of the first command and the second clock request.

11. The clock management circuitry of claim 8, wherein the first slave clock controller is configured to control generating the first clock signal based on a selected one of the first command and the second clock request.

12. The clock management circuitry of claim 8, wherein the first slave clock controller is configured to control generating the first clock signal based on additional information included in at least one of the first command and the second clock request.

13. The clock management circuitry of claim 1, wherein the first slave clock controller is configured to receive the first clock request, and the first slave clock controller is configured to control generating the first clock signal in response to at least one of the first clock request and the first command.

14. The clock management circuitry of claim 1, further comprising:

a second slave clock controller configured to receive a second command via a second channel from the first master clock controller, and configured to control generating a second clock signal based on the second command; and

wherein

the first master clock controller is configured to generate the second command based on the first clock request.

15. The clock management circuitry of claim 14, wherein the first master clock controller is configured to control a sequence in which the first and second clock signals are output by controlling when the first and second commands are output.

16. The clock management circuitry of claim 15, wherein

the first slave clock controller is configured to send a first acknowledgement to the first master clock controller via the first channel in response to outputting the first clock signal;

the second slave clock controller is configured to send a second acknowledgement to the first master clock controller via the second channel in response to outputting the second clock signal; and

the first master clock controller is configured to control outputting a third clock signal after receipt of the first and second acknowledgements.

17. The clock management circuitry of claim 14, wherein

the first slave clock controller is configured to receive a second clock request from a first hardware component via a third channel and is configured to control generating the first clock signal based on the first command and the second clock request;

and

the second slave clock controller is configured to receive a third clock request from a second hardware component via a fourth channel and is configured to control generating the second clock signal based on the second command and the third clock request.

18. The clock management circuitry of claim 14, wherein

the first slave clock controller is configured to receive the first clock request, and the first slave clock controller is configured to control generating the first clock signal in response to at least one of the first clock request and the first command;

and

the second slave clock controller is configured to receive the first clock request, and the second slave clock controller is configured to control generating the second clock signal in response to at least one of the first clock request and the second command.

4. (canceled)

6-7. -7. (canceled)

9. (canceled)

19. (canceled)

20. A system on chip, comprising:

at least first and second hardware components; and

clock management circuitry configured to control supply of first and second clocks to the first and second hardware components, respectively, the clock management circuitry including a first slave clock controller and a first master clock controller, the first master clock controller configured to control operation of the first slave clock controller and configured to control supplying the first clock, and the first slave clock controller configured to control supplying the second clock.

21. The system on chip of claim 20, wherein

the second hardware component is on communication path with the first hardware component;

and

the master clock controller is configured to control the first slave controller to supply the second clock before the master clock controller supplies the first clock.

22. The system on chip of claim 21, further comprising:

a third hardware component; and

a second slave clock controller configured to control supplying a third clock to the third hardware component; and

wherein

the first master clock controller is configured to control operation of the first slave clock controller and the second slave clock controller.

23. The system on chip of claim 22, wherein

the second hardware component and the third hardware component are on a communication path with the first hardware component;

and

the master clock controller is configured to control the first and second slave controllers to supply the second and third clocks before the master clock controller supplies the first clock, and to supply the second and third clocks in a sequence based on an order of the second and third hardware components along the communication path.

24. The system on chip of claim 22, wherein

the master clock controller is configured to send a first command to the first slave controller via a first channel and is configured to send a second command to the second slave controller via a second channel.

25-29. -29. (canceled)

30. A method of clock management, comprising:

receiving a clock request;

supplying a first command to a first slave clock controller via a first channel based on a received first clock request, the first slave clock controller configured to control outputting a first clock based on the first command;

receiving an acknowledgement from the first slave clock controller, the acknowledgement indicating output of the first clock; and

supplying a second clock based on the acknowledgement.