CIRCUIT AND ARCHITECTURE FOR A DEMODULATOR FOR A WIRELESS POWER TRANSFER SYSTEM AND METHOD THEREFOR

• US 20160352146A1
• Filed: 06/06/2016
• Published: 12/01/2016
• Est. Priority Date: 12/16/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Khandelwal, Ashish, Khayat, Joseph M., Su, Yipeng, Neidorff, Robert A., Kannan, Bharath B.
• Granted Patent: US 10,181,754 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/80 involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• CPC Class Codes: H02J 7/00034 Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 2005/00078 Fixed delay
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03K 5/1536 Zero-crossing detectors in measuring circuits G01R19/175
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04B 5/0093 with one coil at each side, e.g. with primary and secondary coils
• CPC Class Codes: H04B 5/02 using transceiver
• CPC Class Codes: H04B 5/266 One coil at each side, e.g. with primary and secondary coils
• CPC Class Codes: H04B 5/48 Transceivers
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Claims

1. (canceled)

11. (canceled)

12. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

17. (canceled)

18. (canceled)

19. (canceled)

20. (canceled)

24. A wireless power transfer system comprising:

a transmitter for transmitting electrical energy through a first inductive coil of a tank circuit, which is electromagnetically coupled to a second inductive coil in a receiver;

the transmitted electrical energy powering or charging device coupled to the receiver;

a circuit in the receiver generating a signal stream which can be recognized the second inductive coil to generate data or command signals in the first conductive coil;

a sample and hold circuit sampling a value of signal in the first conductive coil and holding the value, the sample being taken at a fixed delay from the signal in the first inductive coil; and

a comparator coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream.

2. The controller of claim 24 wherein the delay circuit is a phase delay circuit generates a clock signal which has a phase delay of between 15°

and 75°

with respect to a tank circuit voltage.

3. The controller of claim 24 further comprising a differentiator circuit coupled to the tank circuit for generating a signal related to the slope of the tank circuit voltage.

4. The controller of claim 3 wherein an input signal to the differentiator circuit is a sine wave signal and output thereof is a cosine wave signal.

5. The controller of claim 4 further comprising a zero slope detector coupled between the output of the differentiator circuit in the phase delay circuit.

6. The controller of claim 5 wherein the zero slope detector detects a zero crossing of the cosine wave signal to detect a peak of the tank circuit voltage.

7. The controller of claim 6 wherein the output of the sample and hold circuit is filtered by a low pass filter.

8. The controller of claim 7 wherein output of the low pass filter is compared with an average value of the output of the low pass filter to detect data or commands from the secondary side power receiver.

9. The controller of claim 7 wherein an output of the low pass filter is compared with an output of threshold generating circuit comprising a peak detector circuit and a valley detector circuit and output of the peak detector circuit and output of the valley detector circuit being coupled to an input of a comparator, the other input of which receives the output of the low pass filter.

10. The controller of claim 7 wherein the delay circuit is a phase delay circuit comprising a constant current source;

a first capacitor charged by the constant current source;

a sampling circuit controlled by a clock sampling the voltage across the first capacitor and storing a value of the voltage on a second capacitor;

a resistor divider dividing the voltage across the second capacitor; and

a comparator receiving the voltage across the first capacitor and the voltage across the second capacitor to generate a delayed clock signal.

21. The controller of claim 2 further comprising a buffer circuit coupled between the tank circuit and the sample and hold circuit, the buffer circuit being biased at a DC level near zero volts to increase amplitude of a half sine wave signal at an output thereof.

22. The controller of claim 21 wherein the bias point is substantially 200 mV.

23. The controller of claim 2 further comprising a buffer circuit coupled between the tank circuit and the sample and hold circuit, the buffer circuit being an open loop buffer circuit.