COMMUNICATION OF DEVICE PRESENCE BETWEEN BOOT ROUTINE AND OPERATING SYSTEM

• US 20160371098A1
• Filed: 03/21/2016
• Published: 12/22/2016
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: ESTRADA, DAVID C., ZIMMER, VINCENT J., SAKTHIKUMAR, PALSAMY
• Granted Patent: US 10,002,002 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Claims

1-30. -30. (canceled)

31. An apparatus comprising:

a processor; and

logic, at least partially implemented by the processor, the logic to;

generate a device table comprising a plurality of device blocks, each device block corresponding to one of multiple devices, the device blocks arranged in a hierarchal order within the device table to indicate relative positions of the devices such that a device block corresponding to a core device of the multiple devices precedes all other device blocks; and

load multiple device drivers for the multiple devices in an order that follows the order of the device blocks.

32. The apparatus of claim 31, the hierarchal order to indicate relative positions of the devices in hierarchy of buses and at least one bridge device of the multiple devices.

33. The apparatus of claim 31, the logic to:

detect multiple bridge devices among the multiple devices; and

arrange device blocks of the plurality of device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the processor.

34. The apparatus of claim 31, the logic to:

detect at least one bridge device and at least one endpoint device among the multiple devices; and

arrange device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

35. The apparatus of claim 31, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks.

36. The apparatus of claim 31, the hierarchal order of the plurality of device blocks comprising all device blocks corresponding with core devices preceding all device blocks corresponding with bridge devices further preceding all device blocks corresponding with endpoint devices.

37. The apparatus of claim 31, comprising:

storage to store a hash of the device table; and

the logic to authenticate the device table using the hash of the device table of the device.

38. The apparatus of claim 31, the core device comprising one of a system timer, an interrupt controller, a direct memory access (DMA) controller, a real-time clock, and a cache controller.

39. A computer-implemented method comprising:

generating a device table comprising a plurality of device blocks, each device block corresponding to one of multiple devices, the device blocks arranged in a hierarchal order within the device table to indicate relative positions of the devices such that a device block corresponding to a core device of the multiple devices precedes all other device blocks; and

loading multiple device drivers for the multiple devices in an order that follows the order of the device blocks.

40. The computer-implemented method of claim 39, the hierarchal order to indicate relative positions of the devices in hierarchy of buses and at least one bridge device of the multiple devices.

41. The computer-implemented method of claim 39, comprising:

detecting multiple bridge devices among the multiple devices; and

arranging device blocks of the plurality of device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the core device.

42. The computer-implemented method of claim 39, comprising:

detecting at least one bridge device and at least one endpoint device among the multiple devices; and

arranging device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

43. The computer-implemented method of claim 39, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks.

44. The computer-implemented method of claim 39, the hierarchal order of the plurality of device blocks comprising all device blocks corresponding with core devices preceding all device blocks corresponding with bridge devices further preceding all device blocks corresponding with endpoint devices.

45. The computer-implemented method of claim 39, comprising

retrieving a hash of the device table from memory;

and

authenticating the device table using the hash of the device table of the device.

46. The computer-implemented method of claim 39, the core device comprising one of a system timer, an interrupt controller, a direct memory access (DMA) controller, a real-time clock, and a cache controller.

47. At least one machine-readable storage medium comprising a first sequence of instructions that when executed by a computing device, causes the computing device to:

generate a device table comprising a plurality of device blocks, each device block corresponding to one of multiple devices, the device blocks arranged in a hierarchal order within the device table to indicate relative positions of the devices such that a device block corresponding to a core device of the multiple devices precedes all other device blocks; and

load multiple device drivers for the multiple devices in an order that follows the order of the device blocks.

48. The at least one machine-readable storage medium of claim 47, the hierarchal order to indicate relative positions of the devices in hierarchy of buses and at least one bridge device of the multiple devices.

49. The at least one machine-readable storage medium of claim 47, the computing device caused to:

detect multiple bridge devices among the multiple devices; and

arrange device blocks of the plurality of device blocks corresponding to bridge devices of the multiple bridge devices in the device table in order of decreasing closeness of coupling of each corresponding bridge device to the core device.

50. The at least one machine-readable storage medium of claim 47, the computing device caused to:

detect at least one bridge device and at least one endpoint device among the multiple devices; and

arrange device blocks of the multiple device blocks corresponding to the at least one bridge device and the at least one endpoint device within the device table such that all device blocks corresponding to the at least one bridge device precede all device blocks corresponding to the at least one endpoint device.

51. The at least one machine-readable storage medium of claim 47, each device driver of the multiple device drivers corresponding to a device block of the multiple device blocks.

52. The at least one machine-readable storage medium of claim 47, the hierarchal order of the plurality of device blocks comprising all device blocks corresponding with core devices preceding all device blocks corresponding with bridge devices further preceding all device blocks corresponding with endpoint devices.

53. The at least one machine-readable storage medium of claim 47, the computing device caused to:

retrieve a hash of the device table from memory; and

authenticate the device table using the hash of the device table of the device.

54. The at least one machine-readable storage medium of claim 47, the core device comprising one of a system timer, an interrupt controller, a direct memory access (DMA) controller, a real-time clock, and a cache controller.