INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS

• US 20160371424A1
• Filed: 08/30/2016
• Published: 12/22/2016
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: IYM Technologies LLC (General Patent Corporation)
• Original Assignee: IYM Technologies LLC (General Patent Corporation)
• Inventors: Qian, Qi-De
• Granted Patent: US 9,798,853 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

Claims

1. An integrated circuit (IC) product manufactured using an IC fabrication system by a process comprising:

providing an original design layout;

providing original design rules;

detecting a plurality of areas in the original design layout that have higher manufacturing defect risk if manufactured with the original design rules;

generating location specific constraints for at least the first area in a plurality of areas in the original design layout, wherein one or more of the location specific constraints reduces manufacturing defect risk for the first area;

modifying the original design layout in accordance with the location specific constraints to generate a modified design layout, the modified design layout being different from the original design layout;

providing the modified design layout to the IC fabrication system;

wherein a chip yield exhibited by manufacturing the integrated circuit product by the IC fabrication system using the modified design layout is higher than a chip yield that would be exhibited by the IC fabrication system using the original design layout.

2. The integrated circuit product of claim 1, wherein a dimension of a plurality of first directionally oriented layout objects of a first type of the modified design layout is substantially different from same dimension of second directionally oriented layout objects of the first type, the first directionally oriented layout objects being oriented along a first direction, the second directionally oriented layout objects being oriented along a second direction, the second direction being orthogonal to the first direction.

3. The integrated circuit product of claim 2, wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects reside in the same layer of the modified design layout.

4. The integrated circuit product of claim 3, wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects are conductors.

5. The integrated circuit product of claim 1, wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values.

6. The integrated circuit product of claim 5, wherein the first plurality of routing wires and the second plurality of routing wires reside in the same layer of the modified design layout.

7. The integrated circuit product of claim 1, wherein the original design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances.

8. The integrated circuit product of claim 1, wherein the first area includes interrelated layout objects on one layer.

9. The integrated circuit product of claim 8, wherein the step of generating the location specific constraints comprises comparing known geometry combinations.

10. The integrated circuit product of claim 9, wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table.

11. The integrated circuit product of claim 8, wherein the step of generating the location specific constraints comprises performing pattern recognition.

12. The integrated circuit product of claim 8, wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one interrelated layout object.

13. The integrated circuit product of claim 8, wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent interrelated layout objects.

14. The integrated circuit product of claim 13, wherein the at least two adjacent interrelated layout objects are conductors.

15. The integrated circuit product of claim 1, wherein the step of generating the location specific constraints comprises comparing known geometry combinations.

16. The integrated circuit product of claim 15, wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table.

17. The integrated circuit product of claim 1, wherein the step of generating the location specific constraints comprises performing pattern recognition.

18. The integrated circuit product of claim 1, wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one layout object.

19. The integrated circuit product of claim 1, wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent layout objects.

20. An integrated circuit (IC) product manufactured using an IC fabrication system by a process comprising:

providing an original design layout;

providing original design rules;

providing information regarding an original manufacturing process;

detecting a plurality of areas in the original design layout that have higher manufacturing defect risk if manufactured with the original design rules and the original manufacturing process;

obtaining location specific constraints for at least the first area in a plurality of areas in the original design layout, wherein one or more of the location specific constraints reduces manufacturing defect risk for the first area;

modifying the original design layout or manufacturing process in accordance with the location specific constraints to generate a modified design layout or modified manufacturing process, the modified design layout being different from the original design layout or the modified manufacturing process being different from the original manufacturing process;

providing the modified design layout or modified manufacturing process to the IC fabrication system;

wherein a chip yield exhibited by manufacturing the integrated circuit product by the IC fabrication system using the modified design layout or modified manufacturing process is higher than a chip yield that would be exhibited by the IC fabrication system using the original design layout or original manufacturing process.

21. The integrated circuit product of claim 20, wherein the information regarding the manufacturing process includes information regarding lithography.

22. The integrated circuit product of claim 20, wherein the step of obtaining the location specific constraints comprises using a look-up data table.

23. The integrated circuit product of claim 20, wherein the step of obtaining the location specific constraints comprises using a look-up table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table.

24. The integrated circuit product of claim 20, wherein the step of obtaining the location specific constraints comprises performing pattern recognition.

25. The integrated circuit product of claim 20, wherein the first area includes interrelated layout objects.

26. The integrated circuit product of claim 25, wherein the step of obtaining the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table.

27. The integrated circuit product of claim 25, wherein the step of obtaining the location specific constraints comprises performing pattern recognition.

28. The integrated circuit product of claim 25, wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one interrelated layout object.

29. The integrated circuit product of claim 25, wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent interrelated layout objects.

30. The integrated circuit product of claim 29, wherein the at least two adjacent interrelated layout objects are conductors.