ULTRA LOW PHASE NOISE FREQUENCY SYNTHESIZER
First Claim
1. A system, comprising:
- at least one ultra-low phase noise frequency synthesizer, wherein the at least one ultra-low phase noise frequency synthesizer comprises;
(i) at least one clocking device configured to generate at least one first clock signal of at least one first clock frequency;
(ii) at least one sampling Phase Locked Loop (PLL), wherein the at least one sampling PLL comprises;
(a) at least one sampling phase detector configured to receive the at least one first clock signal and a single reference frequency to generate at least one first analog control voltage; and
(b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one analog control voltage to generate the single reference frequency;
(iii) at least one first fixed frequency divider configured to receive the at least one reference frequency and to divide the at least one reference frequency by a first predefined factor to generate at least one Direct Digital Synthesizer (DDS) clock signal;
(iv) at least one high frequency DDS configured to receive the at least one DDS clock signal and to generate at least one second clock signal of at least one second clock frequency; and
(v) at least one main Phase Locked Loop (PLL), wherein the at least one main PLL comprises;
(a) at least one high frequency Digital Phase/Frequency detector configured to receive and compare the at least one second clock frequency and at least one feedback frequency to generate at least one second analog control voltage and at least one digital control voltage;
(b) at least one main VCO configured to receive the at least one first analog control voltage or the at least one second analog control voltage and generate at least one output signal of at least one output frequency, wherein the at least one digital control voltage controls which of the at least one first analog control voltage or the at least one second analog control voltage is received by the at least one main VCO;
(c) at least one down convert mixer configured to mix the at least one output frequency and the reference frequency to generate at least one intermediate frequency; and
(d) at least one second fixed frequency divider configured to receive and divide the at least one intermediate frequency by a second predefined factor to generate the at least one feedback frequency.
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Accused Products
Abstract
A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.
6 Citations
21 Claims
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1. A system, comprising:
at least one ultra-low phase noise frequency synthesizer, wherein the at least one ultra-low phase noise frequency synthesizer comprises; (i) at least one clocking device configured to generate at least one first clock signal of at least one first clock frequency; (ii) at least one sampling Phase Locked Loop (PLL), wherein the at least one sampling PLL comprises; (a) at least one sampling phase detector configured to receive the at least one first clock signal and a single reference frequency to generate at least one first analog control voltage; and (b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one analog control voltage to generate the single reference frequency; (iii) at least one first fixed frequency divider configured to receive the at least one reference frequency and to divide the at least one reference frequency by a first predefined factor to generate at least one Direct Digital Synthesizer (DDS) clock signal; (iv) at least one high frequency DDS configured to receive the at least one DDS clock signal and to generate at least one second clock signal of at least one second clock frequency; and (v) at least one main Phase Locked Loop (PLL), wherein the at least one main PLL comprises; (a) at least one high frequency Digital Phase/Frequency detector configured to receive and compare the at least one second clock frequency and at least one feedback frequency to generate at least one second analog control voltage and at least one digital control voltage; (b) at least one main VCO configured to receive the at least one first analog control voltage or the at least one second analog control voltage and generate at least one output signal of at least one output frequency, wherein the at least one digital control voltage controls which of the at least one first analog control voltage or the at least one second analog control voltage is received by the at least one main VCO; (c) at least one down convert mixer configured to mix the at least one output frequency and the reference frequency to generate at least one intermediate frequency; and (d) at least one second fixed frequency divider configured to receive and divide the at least one intermediate frequency by a second predefined factor to generate the at least one feedback frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21-50. -50. (canceled)
Specification