Semiconductor Device Structure With 110-PFET and 111-NFET Current Flow Direction

• US 20160379894A1
• Filed: 08/25/2016
• Published: 12/29/2016
• Est. Priority Date: 06/24/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hashemi, Pouya, Khakifirooz, Ali, Mochizuki, Shogo, Reznicek, Alexander
• Granted Patent: US 9,761,499 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence

Abstract

A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.

Claims

1. A method, comprising:

forming a substrate comprising a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer, wherein the top wafer and the handle wafer are arranged such that a <

110>

direction of the (100) silicon of the top wafer aligns with a <

112>

direction of the (110) silicon of the handle wafer;

forming trenches in the top wafer;

forming trenches through the top wafer and into the handle wafer; and

disposing fins in the trenches.

2. The method of claim 1, wherein forming a substrate comprises slicing a wafer of (100) silicon horizontally and bonding the sliced wafer onto the buried oxide layer opposite the handle wafer to form the top wafer.

3. The method of claim 1, wherein forming a substrate comprises slicing a wafer of (110) silicon horizontally and bonding the sliced wafer onto the buried oxide layer opposite the top wafer to form the handle wafer.

4. The method of claim 1, further comprising applying a hardmask layer on the top wafer before forming trenches in the top wafer and before forming trenches through the top wafer and into the handle wafer.

5. The method of claim 1, further comprising forming sidewall spacers on sidewalls of the trenches before disposing fins in the trenches.

6. The method of claim 1, wherein disposing fins in the trenches comprises epitaxially growing fins in the trenches.

7. The method of claim 6, wherein epitaxially growing fins in the trenches comprises using metal-organic chemical vapor deposition to grow a group IV element in the trenches.

8. The method of claim 7, wherein the group IV element comprises 60% boron-doped SiGe or pure Ge.

9. A method of forming a hybrid substrate, the method comprising:

forming an oxide layer on an upper surface of a first substrate comprising (110) silicon;

coupling a lower surface of a second substrate comprising (100) silicon to the oxide layer;

forming a first set of trenches in the second substrate;

forming a second set of trenches through the second substrate and into the first substrate;

forming a first set of fins in the first set of trenches; and

forming a second set of fins in the second set of trenches;

wherein the second substrate and the first substrate are arranged such that a <

110>

direction of the (100) silicon of the second substrate aligns with a <

112>

direction of the (110) silicon of the first substrate.

10. The method of claim 9, wherein the lower surface of the second substrate is coupled to the oxide layer using a layer transfer technique employing a thermal activation process.

11. The method of claim 10, wherein the layer transfer technique comprises slicing the second substrate horizontally and bonding a thin layer of the sliced second substrate onto the oxide layer.

12. The method of claim 9, wherein forming a first set of trenches in the second substrate comprises forming a hardmask layer on an upper surface of the second substrate, the upper surface of the second substrate being opposite the lower surface of the second substrate.

13. The method of claim 12, wherein the hardmask layer is formed using a chemical vapor deposition technique or a physical vapor deposition technique.

14. The method of claim 13, wherein the hardmask layer comprises SiO₂ or a silicon nitride.

15. The method of claim 9, wherein the first set of fins forms a PFET, and wherein the second set of fins forms an NFET.

16. The method of claim 9, wherein forming a first set of trenches and forming a second set of trenches comprises etching.

17. The method of claim 16, wherein etching comprises etching by polyphosphoric acids, by hydrofluoric acid, or by potassium hydroxide.

18. The method of claim 9, further comprising forming sidewall spacers along edges of the first set of trenches and along edges of the second set of trenches before forming a first set of fins in the first set of trenches and before forming a second set of fins in the second set of trenches.

19. The method of claim 9, wherein forming a first set of fins in the first set of trenches and forming a second set of fins in the second set of trenches each comprise growing germanium or SiGe in the first set of trenches and in the second set of trenches using an aspect ratio trapping technique.

20. The method of claim 19, wherein the aspect ratio trapping technique comprises epitaxially growing the germanium or the SiGe using metal-organic chemical vapor deposition.