METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL

• US 20170001861A1
• Filed: 09/14/2016
• Published: 01/05/2017
• Est. Priority Date: 06/27/2011
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: ZHANG, Cerina, LIM, Martin, SHIN, Jongwoo, SEEGER, Joseph
• Granted Patent: US 9,731,963 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/0104 Chemical-mechanical polishing [CMP]
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure

Abstract

Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

Claims

1. A manufacturing method, comprising:

providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer, the second passivation layer having a top surface;

forming an opening in a first portion of the second passivation layer, the opening exposing a portion of a surface of the first passivation layer;

forming a conformal a layer of material over the top surface of the second passivation layer and over the exposed portion of the first passivation layer;

planarizing the conformal layer of material;

patterning the second and first passivation layers to expose portions of the patterned top-level metal layer; and

bonding a second substrate and the first substrate to each other;

wherein the bonding occurs within a temperature range in which at least the exposed portion of the material undergoes outgassing.

2. The method of claim 1, wherein the second passivation layer is disposed on the first passivation layer.

3. The method of claim 1, wherein the first passivation layer comprises silicon oxide and the second passivation layer comprises silicon nitride.

4. The method of claim 1, wherein forming the conformal layer of material comprises exposing the first substrate to a high density plasma.

5. The method of claim 1, wherein forming the conformal layer of material comprises forming an oxide dielectric layer by high density plasma deposition.

6. The method of claim 1, wherein planarizing comprises chemical mechanical planarization (CMP).

7. The method of claim 1, wherein bonding comprises forming an AlGe eutectic.

8. The method of claim 1, wherein bonding the second substrate and the first substrate to each other forms sealed enclosures.

9. The method of claim 8, wherein the sealed cavities are formed before the material undergoes outgassing, and wherein outgassing increases enclosure pressure.

10. The method of claim 9, wherein the first substrate contains transistor circuits.

11. A method of forming a plurality of microelectromechanical system (MEMS)-based sensors having individually set enclosure pressures, comprising:

providing a wafer having transistor circuits thereon, the wafer having a first dielectric layer disposed above a patterned top-level metal layer, and further having a second dielectric layer disposed over the first dielectric layer, the second dielectric layer having a thickness and a top surface;

etching a hole in a second dielectric layer, the etching exposing a portion of a surface of the first dielectric layer;

depositing a blanket layer of high density plasma (HDP) oxide over the second dielectric layer and the hole;

polishing the blanket layer of HDP oxide wherein the second dielectric layer is a polish-stop layer;

forming a first MEMS structure including the hole filled with HDP oxide, and a second MEMS structure excluding the hole filled with HDP oxide; and

eutectically bonding a handle wafer to the first wafer at a temperature high enough to cause the HDP oxide to outgas.

12. The method of claim 11, wherein the first dielectric layer comprises silicon oxide and the second dielectric layer comprises silicon nitride.

13. The method of claim 11, wherein the transistor circuits are complementary metal oxide semiconductor (CMOS) circuits.

14. The method of claim 11, wherein forming the first MEMS structure comprises forming an accelerometer.

15. The method of claim 14, wherein forming the second MEMS structure comprises forming a gyroscope.

16. The method of claim 11, wherein eutectically bonding the handle wafer to the first wafer comprises hermetically sealing the first and the second MEMS structures before the material undergoes outgassing.

17. The method of claim 11, wherein the handle wafer and the first wafer are aligned with each other and brought into contact while in a dry N₂ environment.

18. The method of claim 11, wherein the first dielectric layer is formed by a high density plasma operation.

19. The method of claim 11, wherein forming the first and the second MEMS structures comprises forming a standoff.