METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND RELATED ACTIVE LAYER FOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS

• US 20170005115A1
• Filed: 08/14/2015
• Published: 01/05/2017
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: CHAN, YU CHENG, WANG, ZUQIANG, LIU, CHIEN HUNG, HUANGFU, LUJIANG
• Granted Patent: US 9,887,213 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1281 by using structural features to control crystal growth, e.g. placement of grain filters
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

Claims

1-23. -23. (canceled)

24. A method for forming an active layer with a pattern, comprising:

forming an amorphous silicon layer;

forming a function layer on the amorphous silicon layer, wherein the function layer has a same pattern as the active layer; and

performing a crystallizing process for converting the amorphous silicon layer to a poly-silicon layer, wherein the poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

25. The method according to claim 24, wherein the function layer is made of a non-metal material including silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

26. The method according to claim 24, wherein a thickness of the function layer is about 5 to about 20 nm.

27. The method according to claim 24, further comprising:

applying a mask for patterning the active layer and patterning the function film to form the function layer with the same pattern as the active layer.

28. The method according to claim 24, wherein crystallizing process includes applying an excimer laser annealing process.

29. The method according to claim 24, further including:

forming a buffer layer on a substrate, wherein the buffer layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

30. The method according to claim 29, wherein the substrate is made of glass.

31. The method according to claim 24, wherein the amorphous silicon layer and the function layer are formed consecutively by plasma enhanced chemical vapor deposition.

32. The method according to claim 24, wherein the heat retaining duration for the first portions of the amorphous silicon layer covered by the function layer is longer than or equal to 35 ns.

33. The method according to claim 24, wherein the grain sizes of the poly-silicon formed in the first portions covered by the function layer are about 0.3 to 0.5 μ

m.

34. The method according to claim 24, further comprising:

removing the function layer after crystallizing the amorphous silicon layer and before patterning the poly-silicon layer.

35. The method according to claim 34, wherein removing the function layer includes applying an etching process to remove the function layer.

42. An array substrate, including the thin-film transistor incorporating the active layer formed by the method in claim 24.

43. A display apparatus, including the array substrate incorporating the active layer formed by the method in claim 24.

36. A thin-film transistor, including a substrate, a gate, a source, a drain, an active layer, wherein the active layer is formed by:

forming an amorphous silicon layer;

forming a function layer on the amorphous silicon layer, wherein the function layer has a same pattern as the active layer; and

performing a crystallizing process for converting the amorphous silicon layer to a poly-silicon layer, wherein the poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

37. The thin-film transistor according to claim 36, wherein the thin-film transistor is a top-gate type thin-film transistor.

38. The thin-film transistor according to claim 36, wherein the function layer is formed on the active layer.

39. The thin-film transistor according to claim 36, wherein the function layer is made of a non-metal material including silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

40. A thin-film transistor, including a substrate, a gate, a source, a drain, an active layer, and a function layer, wherein:

the active layer is formed on the substrate;

the function layer is formed on the active layer and has a same pattern as the active layer; and

the drain and the source are electrically connected to the active layer.

41. The thin-film transistor according to claim 40, wherein the drain and the source are electrically connected to the active layer through via-holes.