MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF

• US 20170005195A1
• Filed: 06/30/2015
• Published: 01/05/2017
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Diaz, Carlos H., Wang, Chih-Hao, Lien, Wai-Yi, Leung, Ying-Keung
• Granted Patent: US 9,818,872 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Claims

1. A method of semiconductor device fabrication, comprising:

forming a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition;

removing the second epitaxial layer from the source/drain region of the fin to form a gap;

filling the gap with a dielectric material; and

while the dielectric material is filling the gap, growing another epitaxial material on at least two surfaces of the first epitaxial layer to form a source/drain feature.

2. The method of claim 1, further comprising:

forming a third epitaxial layer underlying the first epitaxial layer;

oxidizing the third epitaxial layer to form an oxidized third epitaxial layer;

wherein the oxidized third epitaxial layer underlies a gate on the channel region and the source/drain feature.

3. The method of claim 1, further comprising:

removing the second epitaxial layer from the channel region of the fin to from another gap; and

forming a gate structure on the first epitaxial layer in the channel region, wherein at least a portion of the gate structure is formed in the another gap.

4. The method of claim 1, further comprising:

prior to forming the fin, performing an anti-punch through (APT) ion implantation into the substrate; and

after performing the APT ion implantation and prior to forming the fin, depositing the first epitaxial layer over the substrate and the second epitaxial layer over the first epitaxial layer.

5. The method of claim 1, further comprising:

forming the first epitaxial layer by growing a silicon layer; and

forming the second epitaxial layer by growing a silicon germanium layer directly on the silicon layer.

6. The method of claim 1, wherein the first epitaxial layer has a first oxidation rate, and wherein the second epitaxial layer has a second oxidation rate greater than the first oxidation rate.

7. The method of claim 1, further comprising:

forming another fin extending from the substrate and having a source/drain region and a channel region, wherein the another fin includes the first epitaxial layer and the second epitaxial layer;

oxidizing the second epitaxial layer of the another fin, while a hard mask layer protects the fin; and

growing a source/drain epitaxial layer on the first epitaxial layer of the another fin, wherein the source/drain epitaxial layers are adjacent the oxidized second epitaxial layer.

8. The method of claim 7, wherein the oxidized second epitaxial layer is greater in thickness than the second epitaxial layer thereby providing a top surface of the first epitaxial layer in the channel region below a top surface of the first epitaxial layer in the source/drain region of the another fin.

9. The method of claim 1, further comprising:

forming a gate structure on the fin, wherein the gate structure is disposed over top, bottom and opposing lateral sides of the first epitaxial layer in the channel region.

10. The method of claim 9, further comprising:

forming a high-k gate dielectric of the gate structure over top, bottom and opposing lateral sides of the first epitaxial layer in the channel region.

11. A method of fabricating a multi-gate device, the method comprising:

growing an epitaxial layer stack including first, second, and third epitaxial layers;

patterning the epitaxial layer stack to form a fin element;

forming a dummy gate structure over the fin element;

transforming the second epitaxial layer in a first region and a second region of the fin to a dielectric layer, wherein the first and second regions are interposed by a third region of the fin, wherein the third region underlies the dummy gate structure;

removing the dummy gate structure after transforming the second epitaxial layer, thereby forming a trench; and

forming a metal gate structure in the trench, wherein the metal gate structure is disposed on multiple sides of each of the first and third epitaxial layers.

12. The method of claim 11, wherein the transforming includes oxidizing the second epitaxial layer in the first region.

13. The method of claim 11, wherein the transforming includes:

removing the second epitaxial layer in the first region to form a gap; and

filling the gap with a dielectric material.

14. The method of claim 11, further comprising:

after removing the dummy gate structure, removing the second epitaxial layer from the third region of the fin to form a gap in the third region.

15. The method of claim 14, wherein a high-k dielectric layer of the metal gate structure is disposed in the gap in the third region.

16. The method of claim 13, further comprising:

forming a fourth epitaxial layer underlying the first, second and third epitaxial layers; and

oxidizing the fourth epitaxial layer to form an oxide layer, wherein the thickness of the oxide layer is greater than the thickness of the dielectric material.

17. A multi-gate semiconductor device, comprising:

a fin element extending from a substrate;

a gate structure extending over a channel region of the fin element, wherein the channel region of the fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure; and

a source/drain region of the fin element adjacent the gate structure, wherein the source/drain region includes;

a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

18. The semiconductor device of claim 17, further including a third semiconductor layer cladding the first and second semiconductor layers and interfacing with a sidewall of the dielectric layer.

19. The semiconductor device of claim 18, wherein the first semiconductor layer includes Si, the dielectric layer includes oxidized SiGe, the second semiconductor layer includes Si.

20. The semiconductor device of claim 18, wherein a high-K gate dielectric of the gate structure is disposed between each of the plurality of channel semiconductor layers.