Method to Reduce Program Disturbs in Non-Volatile Memory Cells

• US 20170011807A1
• Filed: 08/30/2016
• Published: 01/12/2017
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hirose, Ryan T., Kouznetsov, Igor G., Prabhakar, Venkatraman, Shakeri, Kaveh, Georgescu, Bogdan
• Granted Patent: US 9,847,137 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V_NEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Claims

1-20. -20. (canceled)

21. A circuit, comprising:

a memory array including,

a plurality of memory cells, each comprising at least a non-volatile memory (NVM) transistor, arranged in rows and columns, wherein gates of the NVM transistors of memory cells in a same row couple to and share a global wordline; and

a programmable control circuitry coupled to the memory array, wherein the programmable control circuitry includes a voltage control circuitry configured to provide,

a first voltage to a first global wordline in a first row of the memory array, and a second voltage to source-drain paths of memory cells in a first column of the memory array to apply a bias voltage to the NVM transistor in a selected memory cell to program the selected memory cell, and

a third voltage to source-drain paths of memory cells in a second column of the memory array.

22. The circuit of claim 21, wherein each of the plurality of memory cells further includes a first end and a second end, wherein the second ends of memory cells in a same column are coupled to and share a bitline.

23. The circuit of claim 22, wherein the first and second voltages are high voltages and the third voltage is an inhibit voltage (V_INHIB).

24. The circuit of claim 22, wherein the second voltage is provided to the source-drain paths of the memory cells in the first column of the memory array via a first bitline.

25. The circuit of claim 23, wherein the V_INHIB is provided to the source-drain paths of the memory cells in the second column of the memory array via a second bitline, wherein the first bitline is different from the second bitline.

26. The circuit of claim 21, wherein at least one of the plurality of memory cells of the memory array further comprises an insulated-gate field-effect transistor (IGFET) coupled to the NVM transistor in series, wherein a source of the NVM transistor is coupled to the first end and a drain of the IGFET is coupled to the second end of the at least one of the plurality of memory cells, wherein gates of the IGFET in memory cells of the same row are coupled to and share a global read line.

27. The circuit of claim 21, wherein the first voltage and the second voltage have opposite polarities, and the first voltage includes a magnitude that is greater than the second voltage.

28. The circuit of claim 21, wherein the NVM transistors of the plurality of memory cells are n-channel NVM transistors, and wherein the first voltage and the third are positive voltages and the second voltage is a negative voltage.

29. The circuit of claim 21, wherein the programmable control circuitry of claim 21 further comprises:

a programmable digital-to-analog converter (DAC) configured to provide a margin voltage to a second global wordline in a second row of the memory array, wherein the margin voltage includes a magnitude less than the second voltage by at least a threshold voltage (VT) of the NVM transistor in the unselected memory cell.

30. The circuit of claim 21, wherein the first ends of the plurality of memory cells are configured to be coupled to a floating voltage.

31. A method of operating a memory circuit, comprising:

coupling a positive voltage to a first global wordline in a first row of a memory array of memory cells and coupling a negative voltage to first ends of source-drain paths of memory cells in a first column of the memory array to apply a first bias voltage to a non-volatile memory transistor in a selected memory cell to program the selected memory cell; and

coupling a voltage having a magnitude less than the negative voltage to a second global wordline in a second row of the memory array and coupling an inhibit voltage to first ends of source-drain paths of memory cells in a second column of the memory array.

32. The method of claim 31, wherein the inhibit voltage is configured to minimize a second bias voltage applied to a non-volatile memory transistor in an unselected memory cell due to the programming of the selected memory cell.

33. The method of claim 31, wherein the magnitude of the voltage coupled to the second global wordline is less than the negative voltage by an amount at least corresponding to a threshold voltage of a transistor associated with the unselected memory cell.

34. The method of claim 31, further comprising:

generating, by a digital-to-analog converter (DAC), the voltage having the magnitude less than the negative voltage.

35. The method of claim 31, further comprising:

at a first time, coupling the negative voltage to the second global wordline in the second row of the memory array,

wherein the voltage having a magnitude less than the negative voltage is coupled to the second global wordline at a second time.

36. The method of claim 31, wherein the negative voltage is applied to the source-drain paths of the memory cells in the first column of the memory array via a first bitline, and wherein the inhibit voltage is applied to the source-drain paths of the memory cells in the second column of the memory array via a second bitline.

37. The method of claim 35, further comprising:

selecting the first row of the memory array for programming, using a row decoder, by applying the positive voltage to the first global wordline;

deselecting the second row of the memory array for programming, using the row decoder, by applying the voltage having the magnitude less than the negative voltage to the second global wordline; and

selecting the selected memory cell in the first row for programming, using a column decoder, by applying the negative voltage to the first bitline, and to inhibit the unselected memory cell in the first row from the programming by applying the inhibit voltage to the second bitline.

38. The method of 31, further comprising:

coupling second ends of the source-drain paths of the memory cells in the first and second columns to a floating voltage.

39. A memory array, comprising:

a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a non-volatile memory (NVM) transistor, wherein memory cells in a same row share a global wordline, and wherein first ends of memory cells in a same column are coupled to a same bitline, and second ends of the memory cells in the same column are configured to be coupled to a floating voltage,

wherein during programming of a first memory cell associated with a first row and a first column, a positive voltage is applied to a first global wordline associated with the first row and a negative voltage is applied to a first bit line associated with the first column to apply a first bias voltage to a NVM transistor in the first memory cell, while a negative marginal voltage, which has a magnitude less than the negative voltage, is applied to a second global wordline associated with an unselected second row for programming, and an inhibited voltage is applied to a second bitline associated with an unselected second column for programming to minimize a second bias voltage applied to memory cells in the unselected second row and column for programming.

40. The memory array of claim 39, wherein the memory cells in the same column are coupled to a same source line, and wherein memory cells in adjacent columns do not share the same source line.