SYSTEM AND METHOD FOR UPDATING FIRMWARE IN REAL-TIME

• US 20170017485A1
• Filed: 01/06/2016
• Published: 01/19/2017
• Est. Priority Date: 07/17/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ye, Wanfu, Zhou, Xuwei
• Granted Patent: US 9,690,572 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 8/656 while running

Abstract

A system controlled by firmware includes a memory and a processor. The memory includes a first memory block for storing non-programmable code used for performing key functions, and second and third memory blocks for storing programmable code used for performing normal functions. During operation, one of the second and third memory blocks in which the programmable code is being executed is an active memory block. After receiving new programmable code, the processor identifies the inactive memory block, stores the new programmable code therein, and switches to execute the new programmable code while continuing to perform the key functions using the non-programmable code.

Claims

1. A system controlled by firmware, wherein the firmware comprises a set of non-programmable code for performing at least one key function and a set of programmable code for performing at least one normal function, the system comprising:

a memory including;

a first memory block for storing the set of non-programmable code, and

second and third memory blocks that include an active memory block and an inactive memory block, wherein the active memory block stores a first set of programmable code being executed by the system and the inactive memory block stores a second set of programmable code that is not currently being executed by the system; and

a processor, connected to the memory, comprising;

an input unit for receiving a new set of programmable code and a firmware updating request,

a processing unit, connected to the input unit, for executing the set of non-programmable code and the first set of programmable code stored in the active memory block, and

a programming unit, connected to the input unit, wherein the programming unit identifies the inactive memory block and stores the new set of programmable code in the inactive memory block based on said identifying,

wherein after said storing the new set of programmable code in the inactive memory block, the processing unit performs switching from executing the first set of programmable code stored in the active memory block to executing the new set of programmable code in the inactive memory block.

2. The system of claim 1, wherein said storing includes removing the second set of programmable code stored in the inactive memory block.

3. The system of claim 1, wherein the input unit comprises a buffer for buffering a portion of the new set of programmable code, and wherein the programming unit stores the portion of the new set of programmable code in the inactive memory block after a predefined amount of the portion of the new set of programmable code is received in the buffer.

4. The system of claim 1, wherein one of the second and third memory blocks is configured as a default memory block, wherein the processing unit switches to execute the set of programmable code in the default memory block if the processing unit fails to identify the active memory block.

5. The system of claim 4, further comprising a first register that stores a first flag for indicating the active memory block and a second register that stores a second flag for indicating the default memory block, wherein the processor further comprises a control unit connected to the input unit and the processing unit for setting the first and second flags, wherein the active and inactive memory blocks are identified based on the first flag, and wherein the default memory block is identified based on the second flag.

6. The system of claim 1, wherein said switching is performed based on the firmware updating request, wherein the firmware updating request comprises a real-time updating request and a non-real-time updating request, wherein the system comprises a third register for storing a third flag that indicates the updating request is the real-time updating request or the non-real-time updating request, wherein the control unit sets the third flag upon receipt of the firmware updating request.

7. The system of claim 6, wherein the processing unit disables all maskable interrupts except interrupts used in the non-programmable code during said switching if the third flag indicates the real-time updating request, and disables all maskable interrupts during said switching if the third flag indicates the non-real-time updating request.

8. The system of claim 6, wherein the processing unit initializes the system except the non-programmable code during said switching if the third flag indicates the real-time updating request, and initializes the system during said switching if the third flag indicates the non-real-time updating request.

9. The system of claim 1, wherein the memory further comprises a fourth memory block for storing firmware data, wherein the firmware data comprises a set of non-programmable data corresponding to the set of non-programmable code and a set of programmable data corresponding to the set of programmable code being executed by the system.

10. The system of claim 9, wherein the memory comprises a first sub-memory unit including the second memory block, a second sub-memory unit including the first and third memory blocks, and a third sub-memory unit including the fourth memory block and a reserved memory block for storing a copy of the set of non-programmable code when the programming unit is storing the new set of programmable code in the third memory block of the second sub-memory unit or the second memory block of the first sub-memory unit.

11. The system of claim 9, wherein the memory unit comprises a first sub-memory unit including the first, second and third memory blocks, and a second sub-memory unit including the fourth memory block and a reserved memory block for storing a copy of the set of non-programmable code when the programming unit is storing the new set of programmable code into one of the second and third memory blocks of the first sub-memory unit.

12. The system of claim 1, wherein the memory comprises a plurality of sub-memory units, wherein the second and third memory blocks are located in two separate sub-memory units respectively and the first set of programmable code and the second set of programmable code are respectively stored in the two separate sub-memory units from a same address, wherein said switching includes swapping the two separate sub-memory units with each other.

13. A method of updating firmware of a firmware controlled system, wherein the firmware includes a set of non-programmable code for performing at least one key function and a set of programmable code for performing at least one normal function, wherein the system comprises a memory including a first memory block for storing the set of non-programmable code, and second and third memory blocks that include an active memory block storing a first set of programmable code and an inactive memory block storing a second set of programmable code, and wherein the non-programmable code in the first memory block and the first set of programmable code stored in the active memory block are being executed by the system, the method comprising:

identifying the inactive memory block;

storing a new set of programmable code in the inactive memory block; and

after storing the new set of programmable code, switching from executing the first set of programmable code stored in the active memory block to execute the new set of programmable code stored in the inactive memory block based on a firmware updating request,

wherein the system continues to perform the at least one key function during said storing and switching steps.

14. The method of claim 13, wherein said storing includes removing the second set of programmable code stored in the inactive memory block.

15. The method of claim 13, wherein said programming includes buffering a portion of the new set of programmable code and storing the portion of the new set of programmable code in the inactive memory block after a predefined amount of the portion of the new set of programmable code is received.

16. The method of claim 13, further comprising configuring one of the second and third memory blocks as a default memory block, wherein said switching comprises switching to execute the set of programmable code in the default memory block if failing to identify the active memory block.

17. The method of claim 16, wherein the active memory block is identified by reading a first flag that indicates the active memory block, and wherein the default memory block is identified by reading a second flag that indicates the default memory block.

18. The method of claim 13, wherein the firmware updating request comprises a real-time updating request and a non-real-time updating request, wherein said switching comprises disabling all maskable interrupts except interrupts used in the non-programmable code and initializing the system except for the non-programmable code for the real-time updating request, and disabling all maskable interrupts and initializing the system for the non-real-time updating request.

19. The method of claim 13, wherein the first memory block and at least one of the second and third memory blocks are located in one first sub-memory unit of the memory, wherein the method further comprises copying the non-programmable code to a reserved memory block of a second sub-memory unit of the memory before said storing.

20. The method of claim 13, wherein the second and third memory blocks are respectively located in separate sub-memory units of the memory, wherein the first set of programmable code and the second set of programmable code are respectively stored in the separate sub-memory units from a same address, and wherein said switching includes swapping the separate sub-memory units with each other.