Timing Channel Circuitry for Creating Pulses in an Implantable Stimulator Device

• US 20170021181A1
• Filed: 10/10/2016
• Published: 01/26/2017
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Griffith, Paul J., Marnfeldt, Goran N., Parramon, Jordi
• Granted Patent: US 9,925,385 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware

Abstract

Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Claims

1. An implantable stimulator device, comprising:

a memory configured to store pulse parameters for a periodic pulse, wherein each pulse comprises a plurality of sequential pulse phases each with a duration; and

stimulation circuitry configured to sequentially form the pulse phases at electrodes for stimulating a patient'"'"'s tissue, wherein the memory is addressable via an address bus to sequentially provide via a data bus the pulse parameters to the stimulation circuitry,

wherein the pulse parameters for at least one of the pulse phases is stored in a plurality of addresses in the memory.

2. The implantable stimulator device of claim 1, wherein the pulse parameters for the plurality of pulse phases do not comprise the same number of addresses in the memory.

3. The implantable stimulator device of claim 1, wherein a first address in the memory for the pulse parameters for each of the plurality of pulse phases comprises a pre-defined data structure.

4. The implantable stimulator device of claim 3, wherein the first address comprises the duration for each pulse phase.

5. The implantable stimulator device of claim 4, wherein the first address further comprises a command indicative of the number of addresses in which pulse parameters are stored in the memory for each pulse phase.

6. The implantable stimulator device of claim 5, wherein the first address further comprises an address in the memory for a subsequent pulse phase.

7. The implantable stimulator device of claim 1, wherein the pulse parameters comprise amplitude data and active electrode and electrode polarity data for at least some of the plurality of pulse phases.

8. The implantable stimulator device of claim 7, wherein the pulse parameters do not comprise amplitude data and active electrode and electrode polarity data for at least some of the plurality of pulse phases.

9. The implantable stimulator device of claim 1, wherein the plurality of addresses for each pulse phase are sequentially read out of the memory in accordance with a clock.

10. The implantable stimulator device of claim 9, wherein at least some of the pulse parameters are provided to a first register, wherein the first register stores information for addressing the memory and for timing each of the plurality of phases.

11. The implantable stimulator device of claim 9, wherein at least some of the pulse parameters are provided to a second register, wherein the second register provides the at least some of the pulse parameters to the stimulation circuitry in parallel.

12. The implantable stimulator device of claim 1, wherein the plurality of pulse phases are selected from the group consisting of an active phase that actively provides current at the electrodes, a recovery phase for collecting stored charge but which does not actively provide current at the electrodes, and a quite phase that does not actively provide current at the electrodes.

13. The implantable stimulator device of claim 12, wherein the active phase, the recovery phase, and the quite phase are stored in different numbers of addresses in the memory.

14. An implantable stimulator device, comprising:

a memory configured to store pulse parameters for a periodic pulse, wherein each pulse comprises a plurality of sequential pulse phases each with a duration, wherein the pulse parameters for each of the plurality of pulse phases are each stored in at least one address in the memory;

a first register for receiving first data from a first address of the at least one address in the memory for each of the pulse phases;

a second register for receiving second data from other addresses if present of the at least one address in the memory for each of the pulse phases;

control circuitry for receiving the first data, wherein the first data comprises the duration of each of the plurality of phases; and

stimulation circuitry for receiving the second data, wherein the second data configures the stimulation circuitry to form the pulse phases at electrodes for stimulating a patient'"'"'s tissue.

15. The implantable stimulator device of claim 14, wherein the first data further comprises information for addressing the memory, wherein the information for addressing the memory comprises a command indicative of the number of addresses in which pulse parameters are stored in the memory for each pulse phase.

16. The implantable stimulator device of claim 15, wherein the information for addressing the memory further comprises an address in the memory for a subsequent pulse phase.

17. The implantable stimulator device of claim 14, wherein the pulse parameters for each of the plurality of pulse phases do not comprise the same number of addresses in the memory.

18. The implantable stimulator device of claim 14, wherein the second data comprises amplitude data and active electrode and electrode polarity data for at least some of the plurality of pulse phases.

19. The implantable stimulator device of claim 14, wherein the plurality of pulse phases are selected from the group consisting of an active phase that actively provides current at the electrodes, a recovery phase for collecting stored charge but which does not actively provide current at the electrodes, and a quite phase that does not actively provide current at the electrodes.

20. The implantable stimulator device of claim 19, wherein the active phase, the recovery phase, and the quite phase are stored in different numbers of addresses in the memory.