METHOD AND SYSTEM FOR DRIVING AN ACTIVE MATRIX DISPLAY CIRCUIT

• US 20170025065A1
• Filed: 10/07/2016
• Published: 01/26/2017
• Est. Priority Date: 01/09/2006
• Status: Active Application

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, Gholamreza
• Granted Patent: US 10,262,587 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/0272 Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A method and system for driving an active matrix display is provided. The system includes a drive circuit for a pixel having a light emitting device. The drive circuit includes a drive transistor for driving the light emitting device. The system includes a mechanism for adjusting the gate voltage of the drive transistor.

Claims

1-15. -15. (canceled)

16. A display system, the system comprising:

a pixel circuit for being driven to emit light according to programming information during an emission cycle, the pixel circuit comprising;

a light emitting device for emitting light during the emission cycle,

a drive transistor for conveying a drive current through the light emitting device during the emission cycle, said drive transistor having first, second, and gate terminals, a first terminal of said drive transistor coupled to said light-emitting device, and

a regulating transistor for conveying a leakage current to the gate terminal of the drive transistor, thereby adjusting a gate voltage of the drive transistor, said regulating transistor having first, second, and gate terminals,

the first terminal of said regulating transistor being coupled to said gate terminal of said drive transistor,

the second terminal of said regulating transistor being coupled via a first conductive path to a node between said light emitting device and said drive transistor, the conductive path not including the drive transistor and not including the light emitting device, and

the gate terminal of said regulating transistor being coupled via a second conductive path to one of the first and the second terminals of the regulating transistor.

17. The system according to claim 16, wherein the regulating transistor is biased in sub-threshold regime.

18. The system according to claim 17, wherein the first conductive path further comprises:

a first controllable transistor, said second terminal of said regulating transistor being coupled via said first controllable transistor to said node between said light emitting device and said drive transistor.

wherein the gate terminal of said regulating transistor is coupled via the second conductive path to the second terminal of the regulating transistor.

19. The system according to claim 18, wherein the pixel circuit further comprises:

a storage capacitor for being charged with a voltage based at least in part on the programming information during a programming cycle, said storage capacitor having first and second terminals, said first terminal of the storage capacitor being coupled to the gate terminal of the drive transistor, said second terminal of said storage capacitor being coupled to the gate terminal of said regulating transistor,

20. The system according to claim 17, wherein the second conductive path comprises at least a second controllable transistor and wherein the regulating transistor is biased in sub-threshold regime by controllably turning on the second controllable transistor.

21. The system according to claim 20, wherein the pixel circuit further comprises:

a storage capacitor for being charged with a voltage based at least in part on the programming information during a programming cycle, said storage capacitor having first and second terminals, said first terminal of the storage capacitor being coupled to the gate terminal of the drive transistor,

wherein the gate terminal of said regulating transistor is coupled via the second conductive path to the first terminal of the regulating transistor, and

wherein the second controllable transistor has first, second, and gate terminals, the first terminal of the second controllable transistor coupled to the gate terminal of the drive transistor and the second terminal of the second controllable transistor coupled to the first terminal of the regulating transistor.

22. The system according to claim 21, wherein said controllably turning on the second controllable transistor forces the regulating transistor into a linear regime of operation.

23. The system according to claim 22, wherein the pixel circuit further comprises:

a switch transistor having first, second, and gate terminals, the first terminal of the switch transistor coupled to the gate terminal of the drive transistor, the second terminal and the gate terminal of the switch transistor both coupled to one of the first terminal of the regulating transistor and the first conductive path.

24. A method of operating a display having a pixel circuit for driving a light emitting device, the method comprising:

conveying by a drive transistor, a drive current through the light emitting device to emit light during an emission cycle, said drive transistor having first, second, and gate terminals, a first terminal of said drive transistor coupled to said light-emitting device, and

conveying a leakage current by a regulating transistor having first, second, and gate terminals, between the gate terminal of the drive transistor and a node between said light emitting device and said drive transistor, the first terminal of said regulating transistor being coupled to said gate terminal of said drive transistor, the second terminal of said regulating transistor being coupled via a first conductive path to the node, the conductive path not including the drive transistor and not including the light emitting device, and the gate terminal of said regulating transistor being coupled via a second conductive path to one of the first and the second terminals of the regulating transistor.

25. The method according to claim 24, wherein the regulating transistor is biased in sub-threshold regime.

26. The method according to claim 25, wherein the regulating transistor is biased in sub-threshold regime by controllably turning on a first controllable transistor along the second conductive path.

27. The method according to claim 26, wherein controllably turning on the first controllable transistor forces the regulating transistor into a linear regime of operation.

28. The method according to claim 24, further comprising:

detecting energy transfer from the pixel circuit by a sensor.

29. The method according to claim 28, wherein the regulating transistor discharges the voltage at the node according to a conductance of the sensor.

30. The method according to claim 24, wherein conveying a leakage current between the gate terminal of the drive transistor and the node adjusts a voltage of at least one of the gate terminal of the drive transistor and the node.

31. The method according to claim 24, further comprising:

controlling by a second controllable transistor along the first conductive path, at least one of a time said regulating transistor is active and a current of said regulating transistor.