SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS

• US 20170025527A1
• Filed: 04/05/2016
• Published: 01/26/2017
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva, Owyang, King, Kasem, Mohammed, Terrill, Kyle, Katraro, Reuven, Chen, Kuo-In, Choi, Calvin, Chen, Qufei, Wong, Ronald, Lui, Kam Hong, Xu, Robert
• Granted Patent: US 10,032,901 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Claims

1. A semiconductor device comprising:

an electrically conductive substrate layer;

a layer of drain metal, wherein said substrate layer is separated from said drain metal by an intervening layer;

a plurality of gate trenches in a gate region under a layer of source metal and that extend into but not completely through said intervening layer, said gate trenches comprising a first gate trench and a second gate trench, each of said gate trenches filled with a first filler material;

a plurality of source contact trenches in a source region under said layer of source metal and that that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material, said source contact trenches comprising a first source contact trench and a second source contact trench, wherein said first source contact trench is between said first gate trench and said second gate trench, and wherein said second gate trench is between said first source contact trench and said second source contact trench; and

a plurality of feed-through trenches under said layer of drain metal and that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain metal, wherein said plurality of feed-through trenches are arrayed in only a portion of a drain region of said device under said drain metal, wherein said plurality of feed-through trenches are not included outside said portion and wherein said feed-through trenches within said portion are concentrated toward said source region.

2. The semiconductor device of claim 1 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

3. The semiconductor device of claim 1 wherein said feed-through trenches are each lined with a conformal coating that separates said second filler material from said intervening layer.

4. The semiconductor device of claim 3 wherein said conformal coating comprises material selected form the group consisting of:

titanium and titanium nitride.

5. The semiconductor device of claim 3 wherein said conformal coating comprises a thickness of titanium of 60 nanometers (600 Angstroms) and a thickness of titanium-nitride of 20 nanometers (200 Angstroms).

6. The semiconductor device of claim 1 wherein said device comprises a flip chip having a plurality of solder balls formed on a surface thereof, wherein said drain metal is coupled to at least one of said solder balls.

7. The semiconductor device of claim 1 wherein each trench in said plurality of feed-through trenches has a depth of 8.7 microns at their shallowest points, a depth of 9.3 microns at their deepest points, a width of 0.9 microns, and a distance between adjacent feed-through trenches of 1.7 microns.

8. A flip chip semiconductor device comprising:

a plurality of solder balls comprising a solder ball coupled to a layer of drain metal on a first surface of said device;

a first metal layer on a second surface of said device, said second surface opposite said first surface;

a substrate layer adjacent said first metal layer, wherein said substrate layer is separated from said drain metal by an intervening layer;

a plurality of gate trench elements in a gate region under a layer of source metal and that extend into but not completely through said intervening layer, said gate trench elements comprising a first gate trench element and a second gate trench element, each of said gate trench elements filled with a first filler material;

a plurality of source contact trench elements in a source region under said layer of source metal and that extend into but not completely through said intervening layer, each of said source contact trench elements filed with a second filler material, said source contact trench elements comprising a first source contact trench element and a second source contact trench element, wherein said first source contact trench element is between said first gate trench element and said second gate trench element, and wherein said second gate trench element is between said first source contact trench element and said second source contact trench element, and wherein said source contact trench elements are in contact with a layer of source metal but said gate trench elements are isolated from said source metal; and

a plurality of feed-through trench elements that extend completely through said intervening layer to said substrate layer, each of said feed-through trench elements filled with said second filler material and coupled to said drain metal, wherein said feed-through trench elements pass through said intervening layer and into said substrate layer, wherein said plurality of feed-through trench elements are arrayed in only a portion of a drain region of said device under said drain metal, wherein said plurality of feed-through trench elements are not included outside said portion and wherein said feed-through trench elements within said portion are concentrated toward said source region, wherein in operation said device comprises a circuit from a source contact through said intervening layer, said substrate layer, and said feed-through trench elements to said drain metal.

9. The semiconductor device of claim 8 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

10. The semiconductor device of claim 8 wherein said source contact trench elements and said feed-through trench elements are each lined with a conformal coating that separates said second filler material from said intervening layer.

11. The semiconductor device of claim 10 wherein said conformal coating comprises material selected from the group consisting of:

titanium and titanium-nitride.

12. A method of fabricating a flip chip, said method comprising:

forming a plurality of gate trenches in a surface of an epitaxial layer in a gate region of a structure, said gate trenches comprising a first gate trench and a second gate trench, said gate trenches extending partially into but not completely through said epitaxial layer, wherein a plurality of source contact trenches are also formed in said surface of said epitaxial layer in a source region of said structure, said source contact trenches extending partially into but not completely through said epitaxial layer, said source contact trenches comprising a first source contact trench and a second source contact trench, wherein said first source contact trench is between said first gate trench and said second gate trench, and wherein said second gate trench is between said first source contact trench and said second source contact trench;

forming a plurality of feed-through trenches in said surface, said feed-through trenches extending completely through said epitaxial layer and into a substrate layer adjoining a second surface of said epitaxial layer; and

depositing a first filler material into said gate trenches and depositing a second filler material into said source contact trenches and said feed-through trenches, wherein said source contact trenches are subsequently electrically coupled to a first solder ball used as a source contact and wherein said feed-through trenches are subsequently electrically coupled to a second solder ball used as a drain contact, wherein said plurality of feed-through trenches are arrayed in only a portion of a drain region of said flip chip, said drain region under said drain contact, wherein said plurality of feed-through trenches are not included outside said portion and wherein said feed-through trenches within said portion are concentrated toward said source region.

13. The method of claim 12 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

14. The method of claim 12 further comprising, after said source contact trenches and said feed-through trenches are formed and before said second filler material is deposited, depositing a conformal coating that lines said source contract trenches and that lines said feed-through trenches in a same process step.

15. The method of claim 14 wherein said conformal coating comprises material selected from the group consisting of:

titanium and titanium-nitride.