ELECTRONIC DEVICE WITH CAPACITOR BANK LINEARIZATION AND A LINEARIZATION METHOD

• US 20170040943A1
• Filed: 01/08/2016
• Published: 02/09/2017
• Est. Priority Date: 08/06/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: DOARE, Olivier Vincent, SALLE, Didier, PAVAO-MOREIRA, Cristian, GOUMBALLA, Birama
• Granted Patent: US 9,660,578 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01G 15/00 Structural combinations of capacitors or other devices covered by at least two different main groups of this subclass with each other involving at least one hybrid or electric double-layer [EDL] capacitor as the main component H01G11/08
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1293 having means for achieving a desired tuning characteristic, e.g. linearising the frequency characteristic across the tuning voltage range
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. A control circuit coupled to one or more control inputs of the capacitive divider and controllable capacitor bank is configured to modify the equivalent capacitance of the capacitive divider and the controllable capacitor bank for providing capacitance steps, each capacitance step being variable over frequency such that for each step a frequency change Δf of the frequency characteristic is maintained constant in the linearization frequency range.

Claims

1. An electronic device comprising:

a controllable capacitor bank having a bank capacitance comprising a first number of parallel electrically coupled switchable capacitors for controlling a frequency characteristic of the electronic device;

a capacitive divider having a divider capacitance arranged in parallel with the controllable capacitor bank and configured to linearize the controllable capacitor bank in a linearization frequency range of the frequency characteristic, the capacitive divider comprising

a series arrangement of a first series capacitance, and a main capacitor bank comprising a second number of parallel electrically coupled switchable capacitors; and

a control circuit having a plurality of control outputs coupled to a corresponding plurality of control inputs of the capacitive divider and the controllable capacitor bank, the control circuit configured to modify the bank capacitance and the divider capacitance by activating one or more switchable capacitors of the controllable capacitor bank and the main capacitors bank for providing capacitance steps, each capacitance step being variable over frequency such that for each capacitance step a frequency change Δ

f of the frequency characteristic is maintained constant in the linearization frequency range.

2. An electronic device as claimed in claim 1, wherein the controllable capacitor bank and the capacitive divider are arranged such that a smallest divider capacitance is smaller than a smallest bank capacitance.

3. An electronic device as claimed in claim 1, wherein the linearization frequency range is a multiple integer of the frequency change M*Δ

f, M being integer, and the control circuit is configured to

determine a respective capacitance change Δ

C of the capacitive divider associated with the frequency change Δ

f and with a particular frequency within the linearization frequency range.

4. An electronic device as claimed in claim 2, wherein the respective capacitance of one activated capacitor of the capacitive divider is substantially equivalent to said respective capacitance change Δ

C.

5. An electronic device as claimed in claim 1, wherein the capacitive divider comprises a first shunt capacitance having one terminal coupled between the first series capacitance and the main capacitor bank and the other terminal electrically coupled to a reference potential.

6. An electronic device as claimed in claim 5, wherein the capacitive divider further comprises

a second series capacitance electrically coupled in series with the main capacitor bank between the main capacitor bank and the controllable capacitor bank.

7. An electronic device as claimed in claim 6, wherein the capacitive divider further comprises

a second shunt capacitance having one terminal coupled between the main capacitor bank and the second series capacitance and another terminal electrically coupled to the reference potential.

8. The electronic device as claimed in claim 7, wherein the capacitive divider is arranged such that

the first series capacitance is substantially equal to the second series capacitance and the first shunt capacitance is substantially equal to the second shunt capacitance.

9. The electronic device as claimed in claim 1, wherein each switchable capacitor of the main capacitor bank has a unit capacitance, and wherein the first series capacitance and the first shunt capacitance are substantially multiple integer of the unit capacitance.

10. The electronic device as claimed in claim 1, wherein the capacitive divider comprises

a first shunt capacitance having one terminal coupled between the first series capacitance and the main capacitor bank and the other terminal electrically coupled to a reference potential,

a second series capacitance electrically coupled in series with the main capacitor bank between the main capacitor bank and the controllable capacitor bank,

a second shunt capacitance having one terminal coupled between the main capacitor bank and the second series capacitance and another terminal electrically coupled to the reference potential,

each switchable capacitor of the main capacitor bank has a unit capacitance, and wherein the first series capacitance, the second series capacitance, the first shunt capacitance and the second shunt capacitance are substantially multiple integer of the unit capacitance.

11. An electronic device as claimed in claim 1, wherein the main capacitor bank comprises N parallel coupled switchable capacitors, N being integer greater than a number of capacitance steps.

12. The device as claimed in claim 1, wherein the device is a digitally controlled oscillator, the controllable capacitor bank is configured for controlling an output frequency of the digitally controlled oscillator and wherein the capacitive divider is configured for linearizing the controllable capacitor bank.

13. The device as claimed in claim 1, wherein the digitally controlled oscillator is a ring oscillator comprising an odd number of delay stages, each stage having an output being coupled to the controllable capacitor bank and to the capacitive divider for adapting the frequency characteristic of the digitally controlled oscillator and linearizing the controllable capacitor bank.

14. The device as claimed in claim 1, wherein the control circuit comprises a first control circuit configured to control the capacitive divider and a second control circuit configured to control the controllable capacitor bank, wherein the first control circuit comprises

a logic and thermometric decoding controller configured to set a number of parallel coupled switchable capacitors of the main capacitor bank for linearizing the controllable capacitor bank in the linearization frequency range, and

a programmable linearization function configured to determine a linearization vector defining the capacitance step for each frequency change.

15. The device as claimed in claim 1, wherein first series capacitance is a first series varactor or a first series varactor bank of a plurality of parallel coupled varactors, the controllable capacitor bank is a controllable varactor bank of a further plurality of parallel coupled varactors and the main capacitor bank is a main varactor bank of another plurality of parallel coupled varactors.

16. An integrated circuit, comprising at least one electronic device as claimed in claim 1 and a band selection capacitor bank arranged in parallel with the controllable capacitor bank for enabling a frequency trimming of the frequency characteristic to a desired operation frequency range of the electronic device.

17. A method of linearizing a controllable capacitor bank of an electronic device in a linearization frequency range of a frequency characteristic of the electronic device, wherein the controllable capacitor bank has a bank capacitance and comprises a first number of parallel electrically coupled switchable capacitors for controlling the frequency characteristic of the electronic device, the method comprising:

arranging a capacitive divider in parallel with the controllable capacitor bank, wherein the capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank comprising a second number of parallel electrically coupled capacitors,

modifying the bank capacitance and the divider capacitance by activating one or more capacitors of the controllable capacitor bank and the main capacitors bank for providing capacitance steps, each capacitance step being variable over frequency such that for each capacitance step a frequency change Δ

f of the frequency characteristic is maintained constant in the linearization frequency range.

18. The method of claim 17, wherein arranging the capacitive divider comprises providing the capacitive divider with a smallest divider capacitance smaller than a smallest bank capacitance.

19. The method of claim 17, comprising

dividing the linearization frequency range in M, M being integer, equal frequency intervals, each frequency interval corresponding to the frequency change Δ

f, and

determining a respective capacitance change Δ

C associated to the frequency change Δ

f and to a particular frequency within the linearization frequency range.

20. The method of claim 19, wherein

the respective capacitance of one activated capacitor is substantially equivalent to said respective capacitance change Δ

C.