INTELLIGENT VOLTAGE REGULATOR

• US 20170054356A1
• Filed: 08/29/2016
• Published: 02/23/2017
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Inventors: Wright, David G.
• Granted Patent: US 10,162,774 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

Claims

1. A voltage regulator comprising:

a variable voltage generator configured to receive an input voltage and to generate a selected output voltage from a plurality of output voltages based, at least in part, on a selection signal;

a non-volatile memory device configured to store programming instructions to provide the selection signal corresponding to at least first and second power operational states; and

a processing element configured to receive the programming instructions from the non-volatile memory device and to provide the selection signal to the variable voltage generator according to the programming instructions to cause the variable voltage to generate the selected output voltage in accordance with a selected one of the first and second power operational states.

2. The voltage regulator of claim 1 wherein one of the first and second power operational states corresponds to a low-power sleep state.

3. The voltage regulator of claim 2 wherein the processing element is further configured to provide the selection signal to the variable voltage generator according to the programming instructions to cause the variable voltage to generate a lower selected output voltage for the low-power sleep state.

4. The voltage regulator of claim 2 further comprising programming instructions configured to provide a programmable wake up signal to wake from the low-power sleep state.

5. The voltage regulator of claim 4 wherein the programmable wake up signal is configured to be generated in response to user-activation of a system event.

6. The voltage regulator of claim 1 wherein one of the first and second power operational states corresponds to a normal-power state.

7. The voltage regulator of claim 1 further comprising a communication bus input configured to receive an indication of the selected one of the first and second power operational states to thereby generate the selected output voltage.

8. A programmable voltage regulator method, the method comprising:

receiving an input voltage and generating a selected output voltage from a plurality of output voltages based, at least in part, on a selection signal;

storing programming instructions to provide the selection signal corresponding to at least first and second power operational states; and

providing the selection signal according to the programming instructions to cause generation of the selected output voltage in accordance with a selected one of the first and second power operational states.

9. The method claim 8 wherein one of the first and second power operational states corresponds to a low-power sleep state.

10. The method of claim 9 wherein, in response to providing a selection signal corresponding to the low-power sleep state, said generating a selected output voltage comprises generating a lower selected output voltage for the low-power sleep state.

11. The method of claim 9 further comprising waking from the low-power sleep state in response to a programmable wake up signal.

12. The method of claim 11 wherein said waking from the low-power sleep state comprises receiving a user-activation of a system event.

13. The method of claim 8 wherein one of the first and second power operational states corresponds to a normal-power state.

14. The method of claim 8 further comprising receiving at a communication input an indication of the selected one of the first and second power operational states to thereby generate the selected output voltage.