ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA

• US 20170059654A1
• Filed: 11/10/2016
• Published: 03/02/2017
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Granted Patent: US 10,054,638 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Claims

1. An integrated circuit comprising:

(a) a test clock lead capable of receiving a test clock signal;

(b) a test mode select counter lead capable of carrying bidirectional serial data signals and receiving a test mode select signal;

(c) first circuitry having inputs coupled to the test clock lead and to the test mode select counter lead, and having a CE clock output lead for carrying CE clock signals;

(d) counter circuitry having a CE clock input connected to the CE clock output lead, the counter circuitry counting edges of the CE clock signals, a first count output corresponding to a first count of the CE clock signals, a second count output corresponding to a second count of the CE clock signals, a third count output corresponding to a third count of the CE clock signals, and a fourth count output corresponding to a fourth count of the CE clock signals; and

(e) first gating circuitry having inputs connected to the second, and third count outputs and having a selection output lead carrying an output based on the second and third count outputs, and a deselection output lead carrying an output based on the third and fourth outputs; and

(f) second gating circuitry having inputs connected to the first and second count outputs and having a technology specific function output lead carrying an output based on the first and second count outputs.

2. The integrated circuit of claim 1 including adapter test access port circuitry that includes the test clock lead, the test mode select counter lead, the first circuitry, the counter circuitry, and the gating circuitry.

3. The integrated circuit of claim 1 including adapter test access port circuitry that includes the test clock lead, the test mode select counter lead, the first circuitry, the counter circuitry, and the gating circuitry, and including chip level test access port circuitry coupled to the adapter test access port circuitry.