SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170062360A1
• Filed: 08/28/2015
• Published: 03/02/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHANG, SHOU ZEN, LU, CHUN-LIN, WU, KAI-CHIANG, YANG, CHING-FENG, CHEN, VINCENT, WANG, CHUEI-TANG, WANG, YEN-PING, CHEN, HSIEN-WEI, LIN, WEI-TING
• Granted Patent: US 10,727,082 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/1815 Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

Claims

1. A semiconductor device, comprising:

a semiconductor die;

a dielectric material surrounding the semiconductor die to form an integrated semiconductor package;

a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package; and

an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

2. The semiconductor device of claim 1, wherein the path includes a conductive trace connected to the EMI shield at one end, and the conductive trace is a portion of a seal ring of the integrated semiconductor package.

3. The semiconductor device of claim 1, wherein the path includes a conductive through isolation via (TIV), wherein the TIV is extended upwardly from the contact and through the dielectric material.

4. The semiconductor device of claim 1, wherein the path includes a conductive trace embedded in the dielectric material, and the conductive trace is connected to the EMI shield at one end and connected to a conductive through isolation via (TIV) at the other end, wherein the TIV is connected to the contact.

5. The semiconductor device of claim 1, wherein the path includes a conductive retainer in the dielectric material and coupled to the EMI shield, wherein the retainer is proximal to the periphery of the integrated semiconductor package.

6. The semiconductor device of claim 1, further comprising a post passivation interconnect (PPI) over the semiconductor die and the dielectric material, the PPI comprising:

an active portion electrically coupled to the semiconductor die; and

a dummy portion isolated from the semiconductor die, wherein the dummy portion is a portion of the path.

7. The semiconductor device of claim 1, further comprising a plurality of conductive through isolation vias (TIV) in the dielectric material, and each of the plurality of conductive TIV including one end coupled to the contact.

8. The semiconductor device of claim 1, further comprising a plurality of conductive through isolation vias (TIV) in the dielectric material, wherein the plurality of conductive TIV includes at least two different heights, and the plurality of conductive TIV are electrically connected to a plurality of levels of post passivation interconnect (PPI).

9. The semiconductor device of claim 1, wherein a portion of the EMI shield is covering and conformal to a morphology of at least a portion of an outer surface of the integrated semiconductor package.

10. The semiconductor device of claim 1, further comprising an electronic component over and electrically coupled to the semiconductor die through a post passivation interconnect (PPI).

11. A semiconductor device, comprising:

a semiconductor die;

a first molding surrounding a sidewall of the semiconductor die;

a dielectric layer over the molding and the semiconductor die;

a conductive structure in the dielectric layer, wherein the conductive structure includes a conductive trace electrically coupled to the semiconductor die;

a second molding over the dielectric layer, wherein the first molding, the dielectric layer, and the second molding are molded to form an integrated semiconductor package; and

a conductive layer at least covering a portion of an outer surface of the integrated semiconductor package, wherein the conductive layer electrically coupled to a ground terminal of the integrated semiconductor package.

12. The semiconductor device of claim 11, wherein the outer surface is in a stepped configuration.

13. The semiconductor device of claim 11, wherein the outer surface is a tapered surface.

14. The semiconductor device of claim 11, wherein an outer surface of the second molding is in a dome shape and the outer surface of the second molding is covered by the conductive layer.

15. The semiconductor device of claim 11, wherein the conductive structure includes a dummy portion electrically isolated from the semiconductor die and the dummy portion is in a peripheral of the integrated semiconductor package.

16. A method of manufacturing a semiconductor device, comprising

providing a semiconductor die;

surrounding a sidewall of the semiconductor die with a dielectric material;

forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die;

molding the semiconductor die and the PPI into an integrated semiconductor package;

covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface; and

forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

17. The method of claim 16, wherein covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer includes a vapor deposition operation.

18. The method of claim 16, further comprising disposing an electronic component over the PPI, wherein the electronic component is electrically coupled to the semiconductor die through the PPI.

19. The method of claim 16, further comprising forming a conductive trace in the dielectric material, wherein the conductive trace is substantially perpendicular to the sidewall.

20. The method of claim 16, wherein further comprising:

providing a substrate;

disposing a plurality of semiconductor dies on the substrate;

performing a wafer level package operation to form a plurality of integrated semiconductor packages; and

performing a multi-staged cleaving operation to singulate the plurality of integrated semiconductor packages.