MEMORY NETWORK AND SYSTEM INCLUDING THE SAME

• US 20170075578A1
• Filed: 12/21/2015
• Published: 03/16/2017
• Est. Priority Date: 09/15/2015
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Original Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Inventors: KIM, Gwangsun, KIM, John Dongjun, KWON, Yong-Kee
• Granted Patent: US 10,447,584 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: H04L 45/40 Wormhole routing

Abstract

A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Claims

1. A memory network comprising:

a first local memory group comprising a plurality of first memory devices that are not directly connected to each other;

a second local memory group comprising a plurality of second memory devices that are not directly connected to each other; and

a plurality of first channels configured to connect the plurality of first memory devices to the plurality of second memory devices in a one to one relationship.

2. The memory network of claim 1, further comprising a plurality of second channels configured to respectively connect the plurality of first memory devices to a first processor.

3. The memory network of claim 2, further comprising a plurality of third channels configured to respectively connect the plurality of second memory devices to a second processor.

4. The memory network of claim 3, further comprising:

a third local memory group comprising a plurality of third memory devices that are not directly connected to each other;

a plurality of fourth channels configured to connect the plurality of first memory devices to the plurality of third memory devices in a one to one relationship; and

a plurality of fifth channels configured to connect the plurality of second memory devices to the plurality of third memory devices in a one to one relationship.

5. The memory network of claim 4, further comprising a plurality of sixth channels configured to respectively connect the plurality of third memory devices to a third processor.

6. The memory network of claim 5, wherein the first to third processors are CPUs or GPUs.

7. The memory network of claim 5, wherein the first processor is a CPU, and the second and third processors are GPUs.

8. The memory network of claim 7, wherein each of the first memory devices comprises a first pass-thru path, and the first pass-thru path is connected between a first end of a corresponding one of the first channels and a corresponding one of the second channels.

9. The memory network of claim 8, wherein each of the second memory devices comprises a second pass-thru path, and the second pass-thru path is connected between a second end of the corresponding one of the first channels and a first end of a corresponding one of the fifth channels.

10. The memory network of claim 9, wherein in a first routing path including the first pass-thru path, a first data packet associated with the first processor has a higher routing priority than a second data packet associated with the second or third processor.

11. The memory network of claim 10, wherein in a second routing path including the first and second pass-thru paths, a third data packet associated with the first processor has a higher routing priority than a fourth data packet associated with the second or third processor.

12. A system comprising:

a first processor;

a first local memory group comprising a plurality of first memory devices that are not directly connected to each other, the plurality of first memory devices being connected to the first processor through a plurality of respective second channels;

a second processor;

a second local memory group comprising a plurality of second memory devices that are not directly connected to each other, the plurality of second memory devices being connected to the second processor through a plurality of respective third channels; and

a plurality of first channels configured to connect the plurality of first memory devices to the plurality of second memory devices in a one to one relationship.

13. The system of claim 12, further comprising:

a third processor;

a plurality of third memory devices that are not directly connected to each other, the plurality of third memory devices being connected to the third processor through a plurality of respective sixth channels;

a plurality of fourth channels configured to connect the plurality of first memory devices to the plurality of third memory devices in a one to one relationship; and

a plurality of fifth channels configured to connect the plurality of second memory devices to the plurality of third memory devices in a one to one relationship.

14. The system of claim 13, wherein the first to third processors are CPUs or GPUs.

15. The system of claim 13, wherein the first processor is a CPU, and the second and third processors are GPUs.

16. The system of claim 15, wherein each of the first memory devices comprises a first pass-thru path, and the first pass-thru path is connected between a first end of a corresponding one of the first channels and a corresponding one of the second channels.

17. The system of claim 16, wherein each of the second memory devices comprises a second pass-thru path, and the second pass-thru path is connected between a second end of the corresponding one of the first channels and a first end of a corresponding one of the fifth channels.

18. The system of claim 17, wherein in a routing path including the first pass-thru path, a data packet associated with the first processor has a higher routing priority than a data packet associated with the second or third processor.

19. The system of claim 18, wherein in a routing path including the first and second pass-thru paths, a data packet associated with the first processor has a higher routing priority than a data packet associated with the second or third processor.