SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

• US 20170077101A1
• Filed: 11/23/2016
• Published: 03/16/2017
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: INOUE, Hiroki, KATO, Kiyoshi, MATSUZAKI, Takanori, NAGATSUKA, Shuhei
• Granted Patent: US 9,825,037 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Claims

1. (canceled)

2. A semiconductor device comprising:

a line; and

a memory cell comprising a first transistor, a second transistor and a capacitor,

wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,

wherein an insulating layer covers the first transistor,

wherein the insulating layer is over the first channel formation region,

wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the insulating layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,

wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first channel formation region includes silicon, and

wherein the second channel formation region includes an oxide semiconductor.

3. The semiconductor device according to claim 2, wherein the second transistor is provided so as to overlap with at least part of the first transistor.

4. The semiconductor device according to claim 2, wherein an n-channel transistor is used as the second transistor.

5. A semiconductor device comprising:

a line; and

a memory cell comprising a first transistor, a second transistor and a capacitor,

wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,

wherein an insulating layer covers the first transistor,

wherein the insulating layer is over the first channel formation region,

wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the insulating layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,

wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first channel formation region includes silicon,

wherein the second channel formation region includes an oxide semiconductor, and

wherein an off-state current per micrometer of a channel width of the second transistor at room temperature is lower than or equal to 100 zA.

6. The semiconductor device according to claim 5, wherein the second transistor is provided so as to overlap with at least part of the first transistor.

7. The semiconductor device according to claim 5, wherein an n-channel transistor is used as the second transistor.

8. A semiconductor device comprising:

a line; and

a memory cell comprising a first transistor, a second transistor and a capacitor,

wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,

wherein an insulating layer covers the first transistor,

wherein the insulating layer is over the first channel formation region,

wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region over the insulating layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held,

wherein the line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first channel formation region includes silicon,

wherein the second channel formation region includes an oxide semiconductor,

wherein the semiconductor device implements a circuit diagram, and

wherein one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are directly connected to each other in the circuit diagram.

9. The semiconductor device according to claim 8, wherein the second transistor is provided so as to overlap with at least part of the first transistor.

10. The semiconductor device according to claim 8, wherein an n-channel transistor is used as the second transistor.