Three-Dimensional Offset-Printed Memory with Multiple Bits-Per-Cell

• US 20170084348A1
• Filed: 12/06/2016
• Published: 03/23/2017
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 9,741,448 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

Claims

1. A three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell, comprising:

a semiconductor substrate;

at least a memory level stacked above and coupled to said substrate, said memory level comprising at least two data-coding layers storing at least two data-arrays;

wherein all 3D-oP devices in a same 3D-oP batch have a same data-array set; and

at least two 3D-oP devices in said batch have different data-array sequences.

2. The 3D-oP according to claim 1, further comprising a configurable-output for configuring the output of said memory based on the data-array sequence in said memory.

3. The 3D-oP according to claim 2, wherein said configurable-output further comprises a storage means for storing the information related to the data-array sequence.

4. The 3D-oP according to claim 3, wherein said storage means is a non-volatile writable memory.

5. The 3D-oP according to claim 1, wherein said 3D-oP batch further includes first and second 3D-oP devices:

said two data-coding layers of said first 3D-oP device including first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array; and

said two data-coding layers of said second 3D-oP device including third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said fourth data-coding layer storing said first data-array and said third data-coding layer storing said second data-array.

6. The 3D-oP according to claim 5, wherein said first or second 3D-oP device further comprises a configurable-output for configuring the output of said 3D-oP device based on the data-array sequence.

7. The 3D-oP according to claim 1, wherein said 3D-oP batch further includes first and second 3D-oP devices:

said first 3D-oP device comprising first and second memory levels with said second memory level located above said first memory level, said first memory level comprising a first data-coding layer storing said first data-array, said second memory level comprising a second data-coding layer storing said second data-array; and

said second 3D-oP device comprising third and fourth memory levels with said fourth memory level located above said third memory level, said third memory level comprising a third data-coding layer storing said second data-array, said fourth memory level comprising a fourth data-coding layer storing said first data-array.

8. The 3D-oP according to claim 7, wherein said first or second 3D-oP device further comprises a configurable-input for configuring the input of said 3D-oP device based on the data-array sequence.

9. The 3D-oP according to claim 1 belonging to a three-dimensional memory package, wherein said memory package comprises a plurality of vertically stacked 3D-oP dice.

10. The 3D-oP according to claim 1, wherein the total number of data-masks used to form said data-coding layers is fewer than the total number of said data-coding layers.

11. The 3D-oP according to claim 1, wherein the data-patterns in said data-coding layers are formed using photo-lithography.

12. The 3D-oP according to claim 1, wherein the data-patterns in said data-coding layers are formed using imprint-lithography.

13. A batch of three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell, comprising first and second 3D-oP devices, wherein:

said first 3D-oP device comprises a first memory level, said first memory level comprising first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array; and

said second 3D-oP device comprises a second memory level, said second memory level comprising third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said fourth data-coding layer storing said first data-array and said third data-coding layer storing said second data-array.

14. The batch of 3D-oP according to claim 13, wherein said first or second 3D-oP device further comprises a configurable-output for configuring the output of said 3D-oP device based on the data-array sequence.

15. The batch of 3D-oP according to claim 14, wherein said configurable-output further comprises a storage means for storing the information related to the data-array sequence.

16. The batch of 3D-oP according to claim 15, wherein said storage means is a non-volatile writable memory.

17. The batch of 3D-oP according to claim 13 belonging to a three-dimensional memory package, wherein said memory package comprises a plurality of vertically stacked 3D-oP dice.

18. The batch of 3D-oP according to claim 13, wherein the total number of data-masks used to form said data-coding layers is fewer than the total number of said data-coding layers.

19. The batch of 3D-oP according to claim 13, wherein the data-patterns in said data-coding layers are formed using photo-lithography.

20. The batch of 3D-oP according to claim 13, wherein the data-patterns in said data-coding layers are formed using imprint-lithography.