PLATED TERMINATIONS

• US 20170084396A1
• Filed: 11/17/2016
• Published: 03/23/2017
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: Kyocera AVX Components Corporation (Kyocera Corporation)
• Original Assignee: AVX Corporation (Kyocera Corporation)
• Inventors: Ritter, Andrew P., Heistand, II, Robert H., Galvagni, John L., Dattaguru, Sriram
• Granted Patent: US 10,020,116 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/38 Coating with copper
• CPC Class Codes: C23C 18/48 Coating with alloys
• CPC Class Codes: C23C 28/021 including at least one metal alloy layer
• CPC Class Codes: C23C 28/023 only coatings of metal elements only
• CPC Class Codes: C25D 3/56 of alloys
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: C25D 7/00 Electroplating characterised by the article coated
• CPC Class Codes: H01C 1/14 Terminals or tapping points or electrodes specially adapted for resistors in general H01R; Arrangements of terminals or tapping points or electrodes on resistors
• CPC Class Codes: H01C 17/28 adapted for applying terminals
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01C 7/10 voltage responsive, i.e. varistors
• CPC Class Codes: H01F 41/04 for manufacturing coils coils for transformer or inductances H01F27/28
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/12 : Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/228 : Terminals
• CPC Class Codes: H01G 4/232 : electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 : Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H05K 2201/09709 : Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 3/02 : in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: Y10T 29/42 : Piezoelectric device making
• CPC Class Codes: Y10T 29/43 : Electric condenser making
• CPC Class Codes: Y10T 29/435 : Solid dielectric type
• CPC Class Codes: Y10T 29/49002 : Electrical device making
• CPC Class Codes: Y10T 29/49099 : Coating resistive material on a base
• CPC Class Codes: Y10T 29/49101 : Applying terminal

Abstract

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Claims

1-50. -50. (canceled)

51. A method of making a multi-layer electronic component, comprising the steps of:

providing a plurality of dielectric layers, each dielectric layer being delimited laterally by edges;

interleaving a plurality of internal electrode elements among selected of said plurality of dielectric layers, such that selected portions of said plurality of internal electrode elements extend to and are exposed along at least one edge of said plurality of dielectric layers, said interleaved combination of electrode elements and dielectric layers forming a monolithic assembly characterized by respective opposing major surfaces thereof;

providing a plurality of internal anchor tabs interleaved among selected of said plurality of dielectric layers and exposed along selected edges of said plurality of dielectric layers;

configuring said plurality of internal electrode elements in a generally interdigitated configuration with multiple electrode tab portions extending from one or more selected sides of selected internal electrode elements such that the electrode tab portions are exposed at a predetermined number of multiple aligned columns at peripheral locations within a predetermined distance from each other on the multi-layer electronic component;

applying at least a pair of plated terminations over selected of said multiple aligned columns, respectively, of exposed electrode tab portions so that a predetermined distance is formed between such plated terminations; and

wherein said monolithic assembly satisfies the structural relationship of T=about (¼

) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

52. A method of making a multi-layer electronic component as in claim 51, wherein said at least a pair of plated terminations are applied so as to extend over respective end surfaces of said assembly.

53. A method of making a multi-layer electronic component as in claim 51, wherein said at least a pair of plated terminations respectively each form a substantially rectangular region on a respective surface of said assembly.

54. A method of making a multi-layer electronic component, comprising the steps of:

providing a plurality of dielectric layers, each dielectric layer being delimited laterally by edges;

interleaving a plurality of internal electrode elements among selected of said plurality of dielectric layers, such that selected portions of said plurality of internal electrode elements extend to and are exposed along at least one edge of said plurality of dielectric layers, said interleaved combination of electrode elements and dielectric layers forming a monolithic assembly characterized by respective opposing major surfaces thereof;

providing a plurality of internal anchor tabs interleaved among selected of said plurality of dielectric layers and exposed along selected edges of said plurality of dielectric layers;

configuring said plurality of internal electrode elements in a generally interdigitated configuration with multiple electrode tab portions extending from one or more selected sides of selected internal electrode elements such that the electrode tab portions are exposed at a predetermined number of multiple aligned columns at peripheral locations within a predetermined distance from each other of no more than about ten microns for adjacent tab portions in a given aligned column thereof on the multi-layer electronic component;

applying at least a pair of plated terminations over selected of said multiple aligned columns, respectively, of exposed electrode tab portions so that a predetermined distance is formed between such plated terminations; and

wherein said monolithic assembly satisfies the structural relationship of T≦

about (½

) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

55. A method of making a multi-layer electronic component as in claim 54, wherein said monolithic assembly satisfies the structural relationship of T=about (¼

) W to about (½

) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

56. A method of making a multi-layer electronic component as in claim 54, wherein the distance between adjacent of said aligned columns of said exposed electrode tab portions is at least about twice as great as the distance between adjacent tab portions in a given aligned column thereof.

57. A method of making a multi-layer electronic component as in claim 56, wherein the distance between adjacent of said aligned columns of said exposed electrode tab portions is at least about four times as great as the distance between adjacent tab portions in a given aligned column thereof.

58. A method of making a multi-layer electronic component as in claim 54, wherein said at least a pair of plated terminations are applied so as to extend over respective end surfaces of said assembly.

59. A method of making a multi-layer electronic component as in claim 54, wherein said at least a pair of plated terminations respectively each form a substantially rectangular region on a respective surface of said assembly.

60. A method of making a multi-layer electronic component, comprising the steps of:

providing a plurality of dielectric layers, each dielectric layer being delimited laterally by edges;

interleaving a plurality of internal electrode elements among selected of said plurality of dielectric layers, such that selected portions of said plurality of internal electrode elements extend to and are exposed along at least one edge of said plurality of dielectric layers, said interleaved combination of electrode elements and dielectric layers forming a monolithic assembly characterized by respective opposing major surfaces thereof;

providing a plurality of internal anchor tabs interleaved among selected of said plurality of dielectric layers and exposed along selected edges of said plurality of dielectric layers;

configuring said plurality of internal electrode elements in a generally interdigitated configuration with multiple electrode tab portions extending from one or more selected sides of selected internal electrode elements such that the electrode tab portions are exposed at a predetermined number of multiple aligned columns at peripheral locations within a predetermined distance from each other of no more than about ten microns for adjacent tab portions in a given aligned column thereof on the multi-layer electronic component;

applying at least a pair of plated terminations over selected of said multiple aligned columns, respectively, of exposed electrode tab portions so that a predetermined distance is formed between such plated terminations; and

wherein the distance between adjacent of said aligned columns of said exposed electrode tab portions is at least about twice as great as the distance between adjacent tab portions in a given aligned column thereof.

61. A method of making a multi-layer electronic component as in claim 60, wherein the distance between adjacent of said aligned columns of said exposed electrode tab portions is at least about four times as great as the distance between adjacent tab portions in a given aligned column thereof.

62. A method of making a multi-layer electronic component as in claim 60, wherein said monolithic assembly satisfies the structural relationship of T≦

about (½

) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

63. A method of making a multi-layer electronic component as in claim 62, wherein said monolithic assembly satisfies the structural relationship of T=about (¼

) W to about (½

) W, where a dimension of the assembly measured in a direction interconnecting lateral surfaces is W and a dimension thereof measured in a direction interconnecting opposing major surfaces thereof is T.

64. A method of making a multi-layer electronic component as in claim 60, wherein said at least a pair of plated terminations are applied so as to extend over respective end surfaces of said assembly.

65. A method of making a multi-layer electronic component as in claim 60, wherein said at least a pair of plated terminations respectively each form a substantially rectangular region on a respective surface of said assembly.