Core Testing Machine

• US 20170089981A1
• Filed: 09/25/2015
• Published: 03/30/2017
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Contec LLC (Contec LLC /Management/)
• Original Assignee: Contec LLC (Contec LLC /Management/)
• Inventors: Kumar, Samant, Kumar, Dinesh, Diddimani, Shivashankar, Samaiya, Gunjan
• Granted Patent: US 9,810,735 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

A core testing executor/processor for testing a plurality of devices simultaneously using virtualization containers to connect to interfaces of corresponding devices under test is disclosed.

Claims

1. A system for testing devices, the system comprising:

a testing machine with a plurality of slots, wherein each slot of the plurality of slots is for installing a device-under-test (DUT) of a plurality of DUTs;

a plurality of core testing processors, wherein each core testing processor of the plurality of core testing processors is associated with a respective slot of the plurality of slots;

a plurality of lightweight virtualization containers, where a respective lightweight virtualization container of the plurality of lightweight virtualization containers is associated with an interface of a DUT that is installed for testing, wherein the plurality of lightweight virtualization containers enable isolation of respective testing processes and testing resources associated with each respective device-under-test.

2. The system of claim 1, wherein the plurality of lightweight virtualization containers comprise testing probes for testing corresponding interfaces of a respective DUT of the plurality of DUTs.

3. The system of claim 1, wherein the plurality of lightweight virtualization containers are used for testing one or more DUT interfaces at the DUT comprising:

Ethernet Local Area Network (LAN) interface;

Ethernet Wide Area Network (WAN) interface;

Multimedia over Coax Alliance (MoCA) LAN interface;

Multimedia over Coax Alliance (MoCA) WAN interface;

Wireless 2.4 GHz interface;

Wireless 5.0 GHz interface;

Phone ports (FXS) interface;

USB interface;

video interface; and

audio interface.

4. The system of claim 1, wherein each core testing processor of at least a subset of the plurality of core testing processors is associated with a respective web socket for communication that is isolated and independent of communication associated with other core testing processors of the plurality of core testing processors.

5. The system of claim 1, wherein a respective core testing processor of the plurality of core testing processors communicates with a user interface.

6. The system of claim 5, wherein the respective core testing processor of the plurality of core testing processors communicates using asynchronous feedback and interaction.

7. The system of claim 5, wherein the respective core testing processor of the plurality of core testing processors communicates using JSON messages.

8. The system of claim 5, wherein the respective core testing processor of the plurality of core testing processors communicates using TCP/IP protocol.

9. The system of claim 5, wherein the respective core testing processor of the plurality of core testing processors:

retrieves at run time a respective test configuration corresponding to the DUT installed in the respective slot associated with respective core testing processor;

loads the set of tests associated with the DUT installed in the respective slot associated with respective core testing processor; and

executes the loaded set of tests.