ADAPTIVE ASSIGNMENT OF OPEN LOGICAL ERASE BLOCKS TO DATA STREAMS

• US 20170090759A1
• Filed: 09/25/2015
• Published: 03/30/2017
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ioannou, Nikolas, Pletka, Roman A., Tomic, Sasa
• Granted Patent: US 9,886,208 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer-implemented method, according to one embodiment, includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, determining an anticipated throughput of each of the first and second data streams, assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream. Other systems, methods, and computer program products are described in additional embodiments.

Claims

1. A computer-implemented method, comprising:

assigning data having a first heat to a first data stream;

assigning data having a second heat to a second data stream;

determining an anticipated throughput of each of the first and second data streams;

assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream; and

assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.

2. The computer-implemented method of claim 1, wherein the first and second numbers of logical erase blocks assigned to the first and second data streams are proportional to the anticipated throughput thereof.

3. The computer-implemented method of claim 1, wherein the first and/or second number of logical erase blocks are statically assigned to each of the first and/or second data streams.

4. The computer-implemented method of claim 1, wherein the first and/or second number of logical erase blocks assigned to the first and/or second data streams are adjusted dynamically based on a measurement of at least one of:

a temporal stream throughput, and stream stall events of the first and/or second data streams.

5. The computer-implemented method of claim 1, wherein the non-volatile memory includes NAND Flash memory.

6. The computer-implemented method of claim 1, wherein the logical erase blocks are assigned to the data streams in a first-come-first-served fashion.

7. The computer-implemented method of claim 1, wherein the logical erase blocks are assigned to the data streams in a round-robin fashion across all planes of the non-volatile memory.

8. The computer-implemented method of claim 1, comprising:

performing wear leveling on each of the logical erase blocks.

9. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to:

assign, by the controller, data having a first heat to a first data stream;

assign, by the controller, data having a second heat to a second data stream;

determine, by the controller, an anticipated throughput of each of the first and second data streams;

assign, by the controller, a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream; and

assign, by the controller, a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.

10. The computer program product of claim 9, wherein the first and second numbers of logical erase blocks assigned to the first and second data streams are proportional to the anticipated throughput thereof.

11. The computer program product of claim 9, wherein the first and/or second number of logical erase blocks are statically assigned to each of the first and/or second data streams.

12. The computer program product of claim 9, wherein the first and/or second number of logical erase blocks assigned to the first and/or second data streams are adjusted dynamically based on a measurement of at least one of:

a temporal stream throughput, current write amplification, overprovisioning, and stream stall events of the first and/or second data streams.

13. The computer program product of claim 9, wherein the non-volatile memory includes NAND Flash memory.

14. The computer program product of claim 9, wherein the logical erase blocks are assigned to the data streams in a first-come-first-served fashion.

15. The computer program product of claim 9, wherein the logical erase blocks are assigned to the data streams in a round-robin fashion across all planes of the non-volatile memory.

16. The computer program product of claim 9, the program instructions readable and/or executable by the controller to cause the controller to:

perform, by the controller, wear leveling on each of the logical erase blocks.

17. A system, comprising:

a plurality of non-volatile random access memory blocks configured to store data; and

a processor and logic integrated with and/or executable by the processor, the logic being configured to;

assign data having a first heat to a first data stream;

assign data having a second heat to a second data stream;

determine an anticipated throughput of each of the first and second data streams;

assign a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream; and

assign a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream.

18. The system of claim 17, wherein the first and second numbers of logical erase blocks assigned to the first and second data streams are proportional to the anticipated throughput thereof.

19. The system of claim 17, wherein the first and/or second number of logical erase blocks are statically assigned to each of the first and/or second data streams.

20. The system of claim 17, wherein the first and/or second number of logical erase blocks assigned to the first and/or second data streams are adjusted dynamically based on a measurement of at least one of:

a temporal stream throughput, current write amplification, overprovisioning, and stream stall events of the first and/or second data streams.