MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES

• US 20170092370A1
• Filed: 07/26/2016
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Eli Harari
• Inventors: HARARI, Eli
• Granted Patent: US 9,892,800 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface;

a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between second and third semiconductor layers each of a second conductivity type;

a charge-trapping material; and

a plurality of conductors each provided between the first stack of active strip and the second stack of active strips, wherein each conductor is separated from each stack of active strips by the charge-trapping material and extends lengthwise in a second direction that is substantially perpendicular to the planar surface.

2. The memory structure of claim 1, wherein the first, second and third semiconductor layers each comprise polysilicon.

3. The memory structure of claim 1 wherein said first semiconductor layer is P-doped polysilicon and said second and third semiconductor layers are N⁺ doped polysilicon.

4. The memory structure of claim 1, wherein the conductors comprise polysilicon.

5. The memory structure of claim 1, wherein the conductors comprise one of N⁺ doped polysilicon, P⁺ doped Polysilicon, and a refractory metal of a high work function with respect to silicon dioxide.

6. The memory structure of claim 1, wherein each active strip further comprises a metallic layer that is in contact with, and in substantial alignment lengthwise with, the second semiconductor layer.

7. The memory structure of claim 1, wherein the charge-trapping material comprises one or more layers of silicon nitride.

8. The memory structure of claim 7, wherein each layer of silicon nitride is provided between layers of silicon oxide.

9. The memory structure of claim 1 wherein, for each conductor, when a voltage exceeding a predetermined value is applied to the conductor relative to one of the second and third semiconductor layers, the charge-trapping material adjacent the conductor accumulates an electric charge.

10. The memory structure of claim 1, wherein each conductor, the charge-trapping material adjacent the conductor and the first, second and third semiconductor layers form a storage element.

11. The memory structure of claim 10, wherein the storage element comprises a storage transistor in which the conductor serves as a gate terminal of the storage transistor, and the first, second and third semiconductor layers form a channel, source and drain terminals of the storage transistor, respectively.

12. The memory structure of claim 11, wherein two or more of the storage transistors are positioned side by side along said first direction.

13. The memory structure of claim 12 wherein two or more of the storage transistors are formed along both side edges of each of the active strips along said first direction.

14. The memory structure of claim 11 wherein the storage transistors of each active strip share common source and drain terminals but each storage transistor stores charge in-between the channel and the conductor.

15. The memory structure of claim 11, wherein each storage transistor has a native enhancement threshold voltage.

16. The memory structure of claim 11, wherein each conductor serves as the gate terminal of one of the storage transistors in the first stack of active strips and the gate terminal of one of the storage transistors in the second stack of active strips.

17. The memory structure of claim 10, further comprising:

circuitry formed in and on the planar surface of the semiconductor substrate; and

one or more sets of conductive wiring each running along a third direction that is parallel to the planar surface, each conductive wiring connecting the circuits to conductors of one or more of the storage elements.

18. The memory structure of claim 17, wherein the third direction is substantially perpendicular to the first direction.

19. The memory structure of claim 17, wherein a first set of the conductive wiring is provided in a layer substantially parallel the planar surface above both of the first and second stacks of active strips.

20. The memory structure of claim 17, wherein a second set of the conductive wiring is provided in a layer substantially parallel the planar surface between the semiconductor substrate and each of the first and second stacks of active strips.

21. The memory structure of claim 17, wherein the storage elements are each assigned a numeric address, wherein the storage elements assigned an even address is connected by the first set of conductive wiring and wherein the storage elements assigned to an odd address is connected by the second set of conductive wiring.

22. The memory structure of claim 17, wherein the circuitry applies one of the configurations of voltages to cause a selected one or more of the storage elements to provide a current path between the second and the third semiconductor layers associated with each storage element for a predetermined time period, thereby pre-charging the parasitic capacitance of said third semiconductor layer to a selected one of several predetermined voltages, the selected predetermined voltage being selected for one of:

program, program-inhibit, reading and erasing data of the storage element.

23. The memory structure of claim 17, wherein electrical contacts are provided to connect the circuitry to respectively the conductors and one or more of the first, second and third semiconductor layers of each active strip.

24. The memory structure of claim 23, wherein charge stored in the charge-trapping material in each storage element represent data stored in the storage element, wherein the circuitry comprises voltage sources for providing a plurality of configurations of voltages to be imposed on each storage element, so as to effectuate program charging, program-inhibit charging, reading or erasing data stored in the storage element.

25. The memory structure of claim 24, wherein said data represents more than one bit of binary information stored on each storage element.

26. The memory structure of claim 24, wherein said data represents a continuum of stored states in an analog memory.

27. The memory structure of claim 24, wherein the circuits further comprise one or more sense amplifiers for sensing the data stored in the storage elements.

28. The memory structure of claim 24, wherein the storage elements associated with each active strip is organized into one or more NOR strings.

29. The memory structure of claim 24, wherein the storage elements associated with one side of the active strip along the first direction are organized into a first NOR string, and wherein the storage elements associated with the other side of the active strip along the first direction are organized into a second NOR string.

30. The memory structure of claim 29 wherein, during a read or program operation, only the conductor associated with an addressed storage element of a NOR string is momentarily raised to the predetermined voltage required for the read or program operation, with conductors associated all other storage elements of the NOR string held at a voltage below a threshold voltage of an erased storage element.

31. The memory structure of claim 30, wherein active strips on one or more planes other than on a plane associated with the addressed storage element have their second or third semiconductor layer floated or pre-charged to an inhibit voltage.

32. The memory structure of claim 30, wherein storage elements associated with active strips on more than one plane are programmed in a single concurrent programming operation.

33. The memory structure of claim 32 wherein, during the concurrent programming operation, the second or third semiconductor layer of each active strip in each plane is appropriately pre-charged to a predetermined voltage associated with a program or program-inhibit operation, a programming voltage to then apply to one or more addressed conductors, and wherein the concurrent programming operation is terminated after all storage elements associated with the addressed conductors are verified to have reached their respective intended states.

34. The memory structure of claim 33, wherein the programming voltage is one of several programming voltages in a programming sequence, each of the programming voltages representing a different data value.

35. The memory structure of claim 30 wherein the second or third semiconductor layer of each active strip in one or more planes is appropriately concurrently pre-charged to a predetermined voltage associated with a read operation, prior to carrying out one or more read operations of addressed storage elements in one or more of the planes while the second or third semiconductor layer holds the predetermined voltage by virtue of capacitance along its associated active strip.

36. The memory structure of claim 35 wherein the predetermined voltages of active strips on one or more planes serve as virtual ground voltage sources that are isolated from each other, thereby avoiding ground bounce when the addressed storage elements are concurrently read.

37. The memory structure of claim 10, wherein the storage element loses a predetermined portion of the electric charge after a time measured in minutes, hours or days, and wherein the electric charge is read and refreshed for each storage element between time intervals having durations that are shorter than the time for the stored memory state to become corrupted.

38. The memory structure of claim 9, wherein the electric charge is provided from one of the first, second and third semiconductor layers through a Fowler-Nordheim tunneling mechanism.

39. The memory structure of claim 9, wherein the electric charge is provided from one of the first, second and third semiconductor layers through a channel hot-electron mechanism.

40. A semiconductor manufacturing process, comprising:

providing a semiconductor substrate and forming circuitry therein and thereon;

providing a plurality of active layers and buried contacts over the semiconductor substrate, each active layer comprising a first semiconductor layer of a first conductivity between second and third semiconductor layers of a second conductivity, wherein each active layer is electrically isolated from a lower active layer or the semiconductor substrate by a dielectric layer, except at the buried contacts, wherein the buried contacts connect one or more of the second or third semiconductor layers of each active layer to the circuitry of the semiconductor substrate;

patterning and etching the plurality of active layers anisotropically to provide a first set of trenches with sidewalls running lengthwise in a first direction that is substantially parallel to a surface of the semiconductor substrate along a first direction;

providing a charge-trapping material conformally over the sidewalls of the trenches;

filling the trenches with a conductive material; and

patterning and etching a portion of the conductive material, such that the remaining conductive material forms a plurality of conductors that extends lengthwise along a second direction that is substantially perpendicular to the surface of the semiconductor substrate; and

providing a layer of dielectric material over the active layers except at the conductors and a plurality of contacts that is exposed and which is connected to the circuitry in the semiconductor substrate; and

providing conductive wiring that connects the conductors and the exposed contacts.

41. The process of claim 40, wherein the first, second and third semiconductor layers each comprise polysilicon.

42. The process of claim 41, wherein one or both of the second and third semiconductor layers of each active layer are doped in-situ to have the second conductivity.

43. The process of claim 40, wherein the first semiconductor layer of each active layer is ion-implanted to have the first conductivity.

44. The process of claim 43, wherein a single thermal activation step is provided to activate the implanted species in all the active layers.

45. The process of claim 43, wherein the thermal activation step comprises rapid thermal annealing.

46. The process of claim 40, wherein the conductors comprise in-situ doped N⁺ polysilicon or P+ doped polysilicon.

47. The process of claim 40, wherein providing the active layers further comprises providing a metallic layer that is in contact with the second semiconductor layer.

48. The process of claim 40, wherein the charge-trapping material comprises one or more layers of silicon nitride.

49. The process of claim 48, wherein each layer of silicon nitride is provided between layers of other dielectrics, including silicon oxide, aluminum oxide or hafnium oxide.

50. The process of claim 40, further comprising providing a second set of conductive wiring that includes contacts coinciding with the conductors, wherein the step of patterning and etching the trenches expose the contacts such that electrical connection to the conductors is achieved when the conductors are formed.

51. The process of claim 40, wherein the charge-trapping material is provided to have a thickness such that electrons from the first, second and third semiconductor layers tunnel into the charge-trapping material through a Fowler-Nordheim tunneling mechanism when a voltage exceeding a predetermined value is applied across the conductor and the first, second and third semiconductor layers.

52. The process of claim 40, wherein the charge-trapping material is provided to have a thickness such that electrons from one of the second and third semiconductor layers tunnel into the charge-trapping material over the channel through a channel hot-electron injection mechanism when a voltage exceeding a predetermined value is applied across the conductor and one of the second and third semiconductor layers.

53. A NOR string array formed over a planar surface of a semiconductor substrate, comprising a first NOR string and a second NOR string, each NOR string comprising thin-film storage transistors formed along an active strip extending lengthwise along a first direction parallel to the planar surface, wherein the thin film storage transistors in each NOR string share a common drain terminal and a common source terminal, and wherein each storage transistor of the first NOR string is electrically connected to a corresponding storage transistor of the second NOR string by a conductor that extends lengthwise along a second direction which is perpendicular to the planar surface.

54. The NOR string array of claim 53, wherein the active strip of the first NOR string and the active strip of the second NOR string are both formed on a plane parallel to the planar surface.

55. The NOR string array of claim 53, further comprising a third NOR string, wherein the first NOR string and the third NOR string are formed on a plane parallel the planar surface, wherein one or more storage transistors on the third NOR string are programmed to have reference threshold voltages, which are compared to threshold voltages of storage transistors in the first NOR string during programming or read operations.

56. The NOR string array of claim 53, wherein the first NOR string and the second NOR string are formed on first and second planes parallel to the planar surface, respectively, the NOR string array further comprising one or more reference NOR strings on each of the first and second planes, wherein for each reference NOR string, one or more storage transistors on each of the reference NOR strings are programmed to have reference threshold voltages, which are compared to threshold voltages of storage transistors in the one of the first and second NOR strings on the same plane as the reference NOR string, during programming or read operations.

57. The NOR string array of claim 55 wherein the third NOR string provides a reference string leakage current source when all the storage transistors of the third NOR string are in an off state, during reading of a storage transistor in the first NOR string.

58. The NOR string array of claim 56, wherein when the storage transistors of the first NOR string are used as multibit level cells, each state of the multibit levels is stored in a separate reference NOR string.