Semiconductor ESD Protection Device and Method

• US 20170092637A1
• Filed: 09/30/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bakalski, Winfried
• Application Number:
  US14/871,007
• Publication Number:
  US 20170092637A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

According to an embodiment, an electrostatic discharge (ESD) protection circuit includes a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal. The ESD protection circuit further includes a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.

Claims

1. An electrostatic discharge (ESD) protection circuit comprising:

a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal; and

a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.

2. The ESD protection circuit of claim 1, wherein the DC blocking circuit comprises:

a first capacitor coupled between the first input/output node and the third input/output node; and

a second capacitor coupled between the third input/output node and the second input/output node.

3. The ESD protection circuit of claim 1, wherein the DC blocking circuit comprises:

a second transistor having a first source/drain coupled to the first input/output terminal and a gate coupled to the second reference voltage terminal; and

a first capacitor coupled between a second source/drain of the second transistor and the second input/output node.

4. The ESD protection circuit of claim 3, further comprising a second capacitor coupled between the first source/drain of the second transistor and the second source/drain of the second transistor.

5. The ESD protection circuit of claim 1, wherein the first reference voltage terminal is coupled to the ground.

6. The ESD protection circuit of claim 1, further comprising a voltage source having an output coupled to the second reference voltage terminal, the voltage source configured to provide a voltage having an opposite polarity of a threshold voltage of the first transistor.

7. The ESD protection circuit of claim 1, further comprising a resistor coupled between the gate of the first transistor and the second reference voltage terminal.

8. The ESD protection circuit of claim 1, further comprising a second transistor having a first source/drain coupled to the second source/drain of the first transistor, a second source/drain coupled to the first reference voltage terminal, and a gate coupled to the second reference voltage terminal.

9. The ESD protection circuit of claim 1, further comprising the useful circuit.

10. An integrated circuit comprising:

an input pad;

a useful circuit; and

an electrostatic discharge (ESD) protection circuit coupled between the input pad and an input/output terminal of the useful circuit, the ESD protection circuit comprising

a direct current (DC) blocking circuit coupled between the input pad and the input/output terminal of the useful circuit, and

a first transistor having a first source/drain coupled to the input pad, a second source/drain coupled to the ground, and a gate coupled to the DC blocking circuit at a first node; and

a reference voltage source coupled to the gate of the first transistor at the first node, the reference voltage source providing a reference voltage to turn the first transistor off.

11. The circuit of claim 10, wherein the reference voltage source is configured to provide a voltage having an opposite polarity of a threshold voltage of the first transistor.

12. The circuit of claim 10, wherein the ESD protection circuit further comprises a second transistor having a first source/drain coupled to the second source/drain of the first transistor, a second source/drain coupled to the ground, and a gate coupled to the reference voltage source.

13. The circuit of claim 10, wherein the DC blocking circuit comprises:

a first capacitor coupled between the input pad and the first node; and

a second capacitor coupled between the first node and the input/output terminal of the useful circuit.

14. The circuit of claim 10, wherein the DC blocking circuit comprises:

a second transistor having a first source/drain coupled to the input pad and a gate coupled to the reference voltage source; and

a capacitor coupled between a second source/drain of the second transistor and the input/output terminal of the useful circuit.

15. The circuit of claim 10, wherein the ESD protection circuit further comprises a plurality of transistors coupled in series between the first transistor and the ground, a gate of each transistor of the plurality of transistors being coupled to the reference voltage source.

16. The circuit of claim 15, wherein the ESD protection circuit further comprises a plurality of resistors, each resistor of the plurality of resistors being coupled between a corresponding gate of a corresponding transistor of the plurality of transistors and the reference voltage source.

17. The circuit of claim 15, wherein the ESD protection circuit further comprises a plurality of resistors coupled in series between the input pad and the reference voltage source, each resistor of the plurality of resistors being coupled between gates of adjacent transistors of the plurality of transistors.

18. The circuit of claim 10, further comprising a resistor coupled between the gate of the first transistor and the reference voltage source.

19. The circuit of claim 10, wherein the first transistor is an N-type metal-oxide semiconductor field effect transistor.

20. The circuit of claim 10, wherein the reference voltage source comprises a charge pump.

21. A method comprising:

applying a first voltage between a gate terminal and a first source/drain terminal of a first transistor, the first transistor having the first source/drain terminal coupled to a first power supply node and a second source/drain terminal coupled to an input pad of an integrated circuit, wherein the first voltage an a threshold voltage of the first transistor have opposite polarities;

receiving an ESD pulse of a first polarity at the input pad of the integrated circuit; and

turning-on the first transistor upon receipt of the ESD pulse of the first polarity, turning-on the first transistor comprising capacitively coupling the ESD pulse of the first polarity from the input pad of the integrated circuit to the gate terminal of the first transistor.

22. The method of claim 21, further comprising:

applying an AC voltage to the input pad of the integrated circuit; and

capacitively coupling the AC voltage from the input pad to an input of a useful circuit disposed on the integrated circuit.

23. The method of claim 22, wherein:

capacitively coupling the ESD pulse of the first polarity comprises coupling via a first capacitor coupled between the input pad and the gate terminal of the first transistor; and

capacitively coupling the AC voltage comprises coupling via the first capacitor, and via a second capacitor coupled between the gate terminal of the first transistor and the input of the useful circuit.

24. The method of claim 21, further comprising:

receiving an ESD pulse of a second polarity opposite the first polarity at the input pad of the integrated circuit; and

clamping the input pad to the first power supply node via a bulk diode of the first transistor.