DISTRIBUTED CONCATENATED ERROR CORRECTION

• US 20170093438A1
• Filed: 09/25/2015
• Published: 03/30/2017
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: MOTWANI, Ravi H.
• Granted Patent: US 9,912,355 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2936 comprising an outer Reed-Solomon code and an inner convolutional code
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding

Abstract

In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory circuit and an outer error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory controller. In one aspect, it is believed that such an arrangement may be employed to increase the usefulness of memory controllers for later generation memory circuits. Other aspects are described herein.

Claims

1. An apparatus, comprising:

an array of memory cells;

a first integrated circuit die;

a second integrated circuit die having a memory controller electrically coupled to the array of cells of the memory circuit and configured to control the array of memory cells; and

concatenated error correction code logic including an outer error correction code logic disposed on the second integrated circuit die of the memory controller, and having outer error correction code encoder logic configured to encode write data for the array of memory cells in an outer error correction code, and an inner error correction code logic disposed on the first integrated circuit die, and having an inner error correction code encoder logic configured to encode in an inner error correction code, outer error correction code encoded write data from the memory controller so that write data is encoded in concatenated error code comprising the outer error correction code and the inner error correction code.

2. The apparatus of claim 1 further comprising a memory circuit disposed on the first integrated circuit die and including said array of memory cells.

3. The apparatus of claim 2 wherein the inner error correction code logic disposed on the first integrated circuit die of the memory circuit, further has inner error correction decoder logic configured to decode in accordance with the inner error correction code, concatenated encoded read data from the memory circuit which has been encoded in both the outer error correction code and the inner error correction code so that the concatenated encoded read data is decoded with respect to the inner error correction code, and wherein the outer error correction code logic disposed on the second integrated circuit die of the memory controller, further has outer error correction code decoder logic configured to decode in accordance with the outer error correction code, the outer error correction code encoded read data from the memory circuit, which has been encoded in the outer error correction code.

4. The apparatus of claim 3 wherein the concatenated error correction code logic further includes interleaver logic to shuffle outer error code encoded write data from an original order before it is encoded by the inner error correction code logic in the inner error correction code.

5. The apparatus of claim 4 wherein the concatenated error correction code logic further includes de-interleaver logic to restore the original order of the outer error code encoded write data before it is decoded by the outer error correction code decoder logic from the outer error correction code.

6. The apparatus of claim 1 wherein the outer error correction code is a Reed-Solomon error correction code.

7. The apparatus of claim 2 wherein the outer error correction code is a Reed-Solomon error correction code which encodes write data as symbols, and wherein the concatenated error correction code logic includes interleaver logic to shuffle the original order of the symbols encoding the write data for the memory circuit, and de-interleaver logic to restore the original order of the symbols read from the memory circuit.

8. The apparatus of claim 7 wherein the inner error correction code is a convolutional error correction code.

9. A computing system for use with a display, comprising:

a memory;

a processor configured to write data in and read data from the memory;

a video controller configured to display information represented by data in the memory;

wherein the memory includes a memory circuit having an array of memory cells disposed on a first integrated circuit die, and a memory controller disposed on a second integrated circuit die and electrically coupled to the array of cells of the memory circuit and configured to control the array of memory cells; and

concatenated error correction code logic including an outer error correction code logic disposed on the second integrated circuit die of the memory controller, and having outer error correction code encoder logic configured to encode write data for the array of memory cells in an outer error correction code, and an inner error correction code logic disposed on the first integrated circuit die, and having an inner error correction code encoder logic configured to encode in an inner error correction code, outer error correction code encoded write data from the memory controller so that write data is encoded in concatenated error code comprising the outer error correction code and the inner error correction code.

10. The system of claim 9 further comprising a memory circuit disposed on the first integrated circuit die and including said array of memory cells.

11. The system of claim 10 wherein the inner error correction code logic disposed on the first integrated circuit die of the memory circuit, further has inner error correction decoder logic configured to decode in accordance with the inner error correction code, concatenated encoded read data from the memory circuit which has been encoded in both the outer error correction code and the inner error correction code so that the concatenated encoded read data is decoded with respect to the inner error correction code, and wherein the outer error correction code logic disposed on the second integrated circuit die of the memory controller, further has outer error correction code decoder logic configured to decode in accordance with the outer error correction code, the outer error correction code encoded read data from the memory circuit, which has been encoded in the outer error correction code.

12. The system of claim 11 wherein the concatenated error correction code logic further includes interleaver logic to shuffle outer error code encoded write data from an original order before it is encoded by the inner error correction code logic in the inner error correction code.

13. The system of claim 12 wherein the concatenated error correction code logic further includes de-interleaver logic to restore the original order of the outer error code encoded write data before it is decoded by the outer error correction code decoder logic from the outer error correction code.

14. The system of claim 9 wherein the outer error correction code is a Reed-Solomon error correction code.

15. The system of claim 10 wherein the outer error correction code is a Reed-Solomon error correction code which encodes write data as symbols, and wherein the concatenated error correction code logic includes interleaver logic to shuffle the original order of the symbols encoding the write data for the memory circuit, and de-interleaver logic to restore the original order of the symbols read from the memory circuit.

16. The system of claim 15 wherein the inner error correction code is a convolutional error correction code.

17. A method, comprising:

writing data to an array of memory cells disposed on a first integrated circuit die using a memory controller disposed on a second integrated circuit die and concatenated error correction code logic having outer error correction code logic disposed on the second integrated circuit die of the memory controller and having inner error correction code logic disposed on the first integrated circuit die, said writing data including;

encoding write data for the array of memory cells in an outer error correction code using an outer error correction code encoder logic of the outer error correction code logic disposed on the second integrated circuit die of the memory controller, and

encoding the outer error correction code encoded data in an inner error correction code using the inner using an inner error correction code encoder logic of the inner error correction code logic disposed on the first integrated circuit die,

so that write data is encoded in concatenated error code comprising the outer error correction code and the inner error correction code.

18. The method of claim 17 wherein the first integrated circuit die has a memory circuit disposed thereon and includes said array of memory cells.

19. The method of claim 18 further comprising:

decoding concatenated error correction code encoded read data read from the memory cells using an inner error correction decoder logic of the inner error correction code logic disposed on the first integrated circuit die of the memory circuit, so that the concatenated error correction code encoded read data is decoded with respect to the inner error correction code, and

decoding outer error correction code encoded read data using an outer error correction code decoder logic of the outer error correction code logic disposed on the second integrated circuit die of the memory controller, so that the read data is decoded with respect to both the inner error correction code and the outer error correction code.

20. The method of claim 19 further comprising shuffling outer error code encoded write data from an original order before it is encoded by the inner error correction code logic in the inner error correction code, using interleaver logic.

21. The method of claim 20 further comprising restoring the original order of the outer error code encoded write data before it is decoded by the outer error correction code decoder logic from the outer error correction code.

22. The method of claim 17 wherein the outer error correction code is a Reed-Solomon error correction code.

23. The method of claim 18 wherein the encoding write data for the array of memory cells in an outer error correction code using an outer error correction code encoder logic includes encoding the write data in a Reed-Solomon error correction code which encodes write data as symbols, wherein the method further comprises shuffling the original order of the symbols encoding the write data for the memory circuit using an interleaver logic of the concatenated error correction code logic, and wherein the method further comprises restoring the original order of the using de-interleaver logic of the concatenated error correction code logic.

24. The method of claim 23 wherein the inner error correction code is a convolutional error correction code.