Offset-Printing Method for Three-Dimensional Printed Memory with Multiple Bits-Per-Cell

• US 20170098650A1
• Filed: 12/15/2016
• Published: 04/06/2017
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: ZHANG, Guobiao
• Granted Patent: US 9,990,960 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

Claims

1. An offset-printing method for a three-dimensional printed memory with multiple bits-per-cell, comprising the steps of:

1) forming a substrate circuit on a semiconductor wafer, wherein said wafer comprises at least two adjacent dice including first and second dice;

2) a first printing step for transferring a first mask pattern to a first data-coding layer, wherein the origin of said data-mask is initially aligned to the origin of said first die at said first printing step;

3) a second printing step for transferring a second mask pattern to a second data-coding layer above said first data-coding layer, wherein the origin of said data-mask is initially aligned to the origin of said second die at said second printing step;

wherein said first and second mask patterns are located on a same data-mask;

said first and second data-coding layers are formed in a same memory level.

2. The method according to claim 1, where said data-mask comprises at least first and second mask-regions whose mask patterns are transferred to said first and second data-coding layers.

3. The method according to claim 2, where the mask pattern of said first mask-region is transferred to said first data-coding layer in said first die at said first printing step.

4. The method according to claim 2, where the mask pattern of said second mask-region is transferred to said first data-coding layer in said second die at said first printing step.

5. The method according to claim 2, where the mask pattern of said first mask-region is transferred to said second data-coding layer in said second die at said second printing step.

6. The method according to claim 2, where the mask pattern of said second mask-region is transferred to said second data-coding layer in said first die at said second printing step.

7. The method according to claim 2, where said first data-coding layer of said first die stores a first data-array.

8. The method according to claim 2, where said second data-coding layer of said first die stores a second data-array.

9. The method according to claim 2, where said first data-coding layer of said second die stores a second data-array.

10. The method according to claim 2, where said second data-coding layer of said second die stores a first data-array.

11. The method according to claim 1, wherein the displacement between said first and second dice is smaller than the stepping distance of said first printing step.

12. The method according to claim 11, wherein the stepping distance of said first printing step is at least twice the displacement between said first and second dice.

13. The method according to claim 1, wherein the displacement between said first and second dice is smaller than the stepping distance of said second printing step.

14. The method according to claim 13, wherein the stepping distance of said second printing step is at least twice the displacement between said first and second dice.

15. The method according to claim 1, wherein the total number of data-masks is fewer than the total number of data-coding layers.

16. The method according to claim 15, wherein the total number of data-masks is one.

17. The method according to claim 1, wherein said first printing step is photo-lithography.

18. The method according to claim 1, wherein said second printing step is photo-lithography.

19. The method according to claim 1, wherein said first printing step is imprint-lithography.

20. The method according to claim 1, wherein said second printing step is imprint-lithography.