APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY

• US 20170109281A1
• Filed: 12/29/2016
• Published: 04/20/2017
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Boris Ginzburg, Eliezer Weissmann, Karthikeyan Karthik Vaithianathan, Ronny Ronen, Yoav Zach
• Original Assignee: Boris Ginzburg, Eliezer Weissmann, Karthikeyan Karthik Vaithianathan, Ronny Ronen, Yoav Zach
• Inventors: WEISSMANN, ELIEZER, VAITHIANATHAN, KARTHIKEYAN KARTHIK, ZACH, YOAV, GINZBURG, BORIS, RONEN, RONNY
• Granted Patent: US 9,971,688 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 2212/684 : TLB miss handling
• CPC Class Codes: G06F 3/0646 : Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0662 : Virtualisation aspects
• CPC Class Codes: G06F 3/0668 : adopting a particular infrastructure
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3881 : Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]

Abstract

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Claims

1. A system comprising:

a plurality of simultaneous multithreading (SMT) cores to perform out-of-order instruction execution for a plurality of threads;

a memory hierarchy comprising a system memory and a plurality of cache levels coupled to one or more of the SMT cores;

an accelerator to perform data operations associated with one or more tasks, the accelerator comprising;

an accelerator functional unit; and

context save/restore circuitry to save and restore a context of the accelerator functional unit; and

front end hardware logic coupled to the accelerator, the front end hardware logic to receive and schedule tasks for execution on the accelerator, the front end hardware logic comprising;

a translation lookaside buffer (TLB) to store virtual-to-physical address mappings; and

page walker circuitry to provide page walk services to the accelerator to determine virtual-to-physical address mappings.

2. The system of claim 1 wherein the front end hardware logic further comprises:

address translation circuitry to perform a virtual-to-physical address translation for one or more of the accelerator execution circuits by querying the TLB containing the mapping of virtual-to-physical addresses.

3. The system as in claim 2 wherein the address translation circuitry is to cause the page walker circuitry to access a page table from the memory hierarchy if the query to the TLB fails to locate a translation for a particular virtual address.

4. The system as in claim 3 wherein the front end hardware logic is to access the memory hierarchy of the one or more processor cores using the address translation.

5. The system as in claim 3 wherein the plurality of cache levels include a first cache integral to at least one processor core and a second cache to be shared by two or more of the processor cores.

6. The system as in claim 1 wherein the front end hardware logic is to detect a shootdown operation for a restricted page, the front end hardware logic to flush one or more entries in the TLB responsive to detecting the shootdown operation.

7. The system as in claim 1 further comprising:

a communication interface to couple the front end hardware logic to one or more processor cores.

8. The system as in claim 7 wherein the communication interface comprises a Peripheral Component Interconnect Express (PCIe) interface.

9. The system as in claim 1 wherein at least one of the SMT cores comprises:

an instruction fetch circuit to fetch instructions of the one or more threads;

an instruction decode circuit to decode the instructions;

a register renaming circuit to rename registers of a register file;

an instruction cache circuit to store instructions to be executed;

a data cache circuit to store data;

at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit.

10. A computer-readable medium having stored thereon hardware description language code to implement:

a plurality of simultaneous multithreading (SMT) cores to perform out-of-order instruction execution for a plurality of threads;

a memory hierarchy comprising a system memory and a plurality of cache levels coupled to one or more of the SMT cores;

an accelerator to perform data operations associated with one or more tasks, the accelerator comprising;

an accelerator functional unit, and

context save/restore circuitry to save and restore a context of the accelerator functional unit, and

front end hardware logic coupled to the accelerator, the front end hardware logic to receive and schedule tasks for execution on the accelerator, the front end hardware logic comprising;

a translation lookaside buffer (TLB) to store virtual-to-physical address mappings, and

page walker circuitry to provide page walk services to the accelerator to determine virtual-to-physical address mappings.

11. The computer-readable medium of claim 10 wherein the front end hardware logic further comprises:

address translation circuitry to perform a virtual-to-physical address translation for one or more of the accelerator execution circuits by querying the TLB containing the mapping of virtual-to-physical addresses.

12. The computer-readable medium as in claim 11 wherein the address translation circuitry is to cause the page walker circuitry to access a page table from the memory hierarchy if the query to the TLB fails to locate a translation for a particular virtual address.

13. The computer-readable medium as in claim 12 wherein the front end hardware logic is to access the memory hierarchy of the one or more processor cores using the address translation.

14. The computer-readable medium as in claim 12 wherein the plurality of cache levels include a first cache integral to at least one processor core and a second cache to be shared by two or more of the processor cores.

15. The computer-readable medium as in claim 10 wherein the front end hardware logic is to detect a shootdown operation for a restricted page, the front end hardware logic to flush one or more entries in the TLB responsive to detecting the shootdown operation.

16. The computer-readable medium as in claim 10 further comprising hardware description language code to implement:

a communication interface to couple the front end hardware logic to one or more processor cores.

17. The computer-readable medium as in claim 16 wherein the communication interface comprises a Peripheral Component Interconnect Express (PCIe) interface.

18. The computer-readable medium as in claim 10 wherein at least one of the SMT cores comprises:

an instruction fetch circuit to fetch instructions of the one or more threads;

an instruction decode circuit to decode the instructions;

a register renaming circuit to rename registers of a register file;

an instruction cache circuit to store instructions to be executed;

a data cache circuit to store data;

at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit.