NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF

• US 20170123870A1
• Filed: 09/15/2016
• Published: 05/04/2017
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: TAI, Ying Yu, ZHU, Jiangli
• Granted Patent: US 10,303,536 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a second time point and then performs a patrol read on a portion of the closed blocks according to the ratio value.

Claims

1. A non-volatile memory device, comprising:

a non-volatile memory comprising a plurality of closed blocks and a plurality of open blocks; and

a controller deriving a ratio value according to a write workload of the non-volatile memory between a first time point and a second time point and performing a patrol read on a portion of the closed blocks according to the ratio value.

2. The non-volatile memory device as claimed in claim 1, wherein the patrol read is to determine a bit error rate (BER) for each of the portion of the closed blocks, and when the BER of a first closed block among the portion of the closed blocks exceeds a tolerance value, the controller moves valid data of the first closed block to at least one of the open blocks and erases the first closed block.

3. The non-volatile memory device as claimed in claim 2, wherein when the BER of the first closed block exceeds the tolerance value, the controller moves the valid data and invalid data of the first closed block to at least one of the open blocks and erases the first closed block.

4. The non-volatile memory device as claimed in claim 1, wherein the write workload is a number of blocks which are filled when the non-volatile memory operates between the first and second time points.

5. The non-volatile memory device as claimed in claim 1, wherein the first time point is a time point when a previous patrol read has been performed, and the second time point is a time point when a next patrol read is ready to be performed.

6. The non-volatile memory device as claimed in claim 1, wherein the controller determines an original block which is filled first after the first time point and determines a final block which is filled last before the second time point.

wherein the controller derives the ratio value according to property parameters of the original block and the final block, and determines the number of portion of the closed blocks on which the patrol read is performed according to the ratio value.

7. The non-volatile memory device as claimed in claim 6, wherein the property parameters include indexes or time stamps of the original block and the final block.

8. The non-volatile memory device as claimed in claim 1, wherein the controller determines the number of portion of the closed blocks by multiplying the ratio value by the number of all of the closed blocks.

9. The non-volatile memory device as claimed in claim 1, wherein the controller determines an oldest closed block according to a BER, a program/erase (P/E) cycle count, a fail bit count (FBC), or a retention time of each of the closed blocks, and performs the patrol read on the portion of the closed blocks from the oldest closed block.

10. The non-volatile memory device as claimed in claim 1, wherein when the non-volatile memory is switched from a power-off status to a power-on status, the controller performs the patrol read on all of the closed blocks.

11. A control method applied to a non-volatile memory comprising a plurality of closed blocks and a plurality of open blocks, comprising:

deriving a ratio value according to a write workload of the non-volatile memory between a first time point and a second point; and

performing a patrol read on a portion of the closed blocks according to the ratio value.

12. The control method as claimed in claim 11, wherein the step of performing the patrol read on the portion of the closed blocks according to the ratio value comprises:

determining a bit error rate (BER) of each of the portion of the closed blocks, wherein when the BER of a first closed block among the portion of the closed blocks exceeds a tolerance value, valid data of the first closed block is moved to at least one of the open blocks and the first closed block is erased.

13. The control method as claimed in claim 12, wherein when the BER of the first closed block exceeds the tolerance value, the valid data and invalid data of the first closed block are moved to at least one of the open blocks and the first closed block is erased.

14. The control method as claimed in claim 11, wherein the write workload is the number of blocks which are filled when the non-volatile memory operates between the first and second time points.

15. The control method as claimed in claim 11, wherein the first time point is a time point when a previous patrol read has been performed, and the second time point is a time point when a next patrol read is ready to be performed.

16. The control method as claimed in claim 11, wherein the step of deriving the ratio value according to the write workload of the non-volatile memory between the first time point and the second point comprises:

determining an original block which is filled first after the first time point;

determining a final block which is filled last before the second time point;

deriving the ratio value according to property parameters of the original block and the final block; and

determining the number of portion of the closed blocks on which the patrol read is performed according to the ratio value.

17. The control method as claimed in claim 16, wherein the property parameters include indexes or time stamps of the original block and the final block.

18. The control method as claimed in claim 11, further comprising:

multiplying the ratio value by the number of all of the closed blocks to determine the number of portion of the closed blocks.

19. The control method as claimed in claim 11, further comprising:

determining an oldest closed block according to a BER, a program/erase (P/E) cycle count, a fail bit count (FBC), or a retention time of each of the closed blocks; and

performing the patrol read on the portion of the closed blocks from the oldest closed block.

20. The control method as claimed in claim 11, further comprising:

performing the patrol read on all of the closed blocks when the non-volatile memory is switched from a power-off status to a power-on status.