Data Storage Method and Phase Change Memory

• US 20170133089A1
• Filed: 01/23/2017
• Published: 05/11/2017
• Est. Priority Date: 07/24/2014
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Li, Zhen, Miao, Xiangshui, Xu, Ronggang, Zhao, Junfeng, Zhang, Shujie, He, Qiang
• Granted Patent: US 9,899,084 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

Claims

1. A data storage method applying to a phase change memory, comprising:

obtaining a first to-be-stored data, wherein the first to-be-stored data is multi-bit data;

generating a first erase pulse signal and a first write pulse signal according to the first to-be-stored data, wherein the first write pulse signal is a signal comprising at least two consecutive pulses, wherein the at least two consecutive pulses have a same amplitude, and wherein the amplitude of the at least two consecutive pulses is a value determined according to the first to-be-stored data;

applying the first erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state; and

applying the first write pulse signal to the storage unit to allow the storage unit to switch to a first amorphous state corresponding to a first resistance value, wherein the first amorphous state represents the first to-be-stored data.

2. The method according to claim 1, wherein the at least two consecutive pulses in the first write pulse signal have a same pulse width.

3. The method according to claim 1, further comprising:

obtaining a second to-be-stored data which is different from the first to-be-stored data, wherein the quantity of the bits in the second to-be-stored data equals to the quantity of the bits in the first to-be-stored data;

generating a second erase pulse signal and a second write pulse signal according to the second to-be-stored data, wherein the second write pulse signal is a signal comprising at least two consecutive pulses with a same amplitude, wherein the amplitude of the at least two consecutive pulses in the second write pulse signal is a value determined according to the second to-be-stored data, and wherein the amplitude of the at least two consecutive pulses in the second write pulse signal is different from the amplitude of the at least two consecutive pulses in the first write pulse signal;

applying the second erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state; and

applying the second write pulse signal to the storage unit to allow the storage unit to switch to a second amorphous state corresponding to a second resistance value, wherein the second amorphous state represents the second to-be-stored data.

4. The method according to claim 1, further comprising:

obtaining a third to-be-stored data, wherein the third to-be-stored data equals to a preset multi-bit data, and wherein each bit in the third to-be-stored data is same;

generating a third erase pulse signal according to the third to-be-stored data; and

applying the third erase pulse signal to the storage unit to allow the storage unit to switch to a crystalline state, wherein the crystalline state of the storage unit represents the third to-be-stored data.

5. The method according to claim 2, wherein a pulse width range of the at least two consecutive pulses in the first write pulse signal is 30 nanoseconds (ns) to 50 ns.

6. The method according to claim 1, wherein a range of an interval between the at least two consecutive pulses in the first write pulse signal is 5 ns to 15 ns.

7. The method according to claim 1, wherein the first write pulse signal is a voltage signal comprising at least two consecutive pulses, and an amplitude range of each of the at least two consecutive pulses in the first write pulse signal is 0.5 volt (V) to 1.5 V.

8. A phase change memory, comprising a storage unit and a controller coupled to the storage unit, wherein the controller is configured to:

obtain a first to-be-stored data, wherein the first to-be-stored data is multi-bit data;

generate a first erase pulse signal and a first write pulse signal according to the first to-be-stored data, wherein the first write pulse signal is a signal comprising at least two consecutive pulses, wherein the at least two consecutive pulses have a same amplitude, and wherein the amplitude of the at least two consecutive pulses is a value determined according to the first to-be-stored data;

apply the first erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state; and

apply the first write pulse signal to the storage unit to allow the storage unit to switch to a first amorphous state corresponding to a first resistance value, wherein the first amorphous state represents the first to-be-stored data.

9. The phase change memory according to claim 8, wherein the at least two consecutive pulses in the first write pulse signal have a same pulse width.

10. The phase change memory according to claim 8, wherein the controller is further configured to:

obtain a second to-be-stored data which is different from the first to-be-stored data, wherein the quantity of the bits in the second to-be-stored data equals to the quantity of the bits in the first to-be-stored data;

generate a second erase pulse signal and a second write pulse signal according to the second to-be-stored data, wherein the second write pulse signal is a signal comprising at least two consecutive pulses with a same amplitude, wherein the amplitude of the at least two consecutive pulses in the second write pulse signal is a value determined according to the second to-be-stored data, and wherein the amplitude of the at least two consecutive pulses in the second write pulse signal is different from the amplitude of the at least two consecutive pulses in the first write pulse signal;

apply the second erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state; and

apply the second write pulse signal to the storage unit to allow the storage unit to switch to a second amorphous state corresponding to a second resistance value, wherein the second amorphous state represents the second to-be-stored data.

11. The phase change memory according to claim 8, wherein the controller is further configured to:

obtain a third to-be-stored data, wherein the third to-be-stored data equals to a preset multi-bit data, and wherein each bit in the third to-be-stored data is same;

generate a third erase pulse signal according to the third to-be-stored data; and

apply the third erase pulse signal to the storage unit to allow the storage unit to switch to a crystalline state, wherein the crystalline state of the storage unit represents the third to-be-stored data.

12. The phase change memory according to claim 9, wherein a pulse width range of the at least two consecutive pulses in the first write pulse signal is 30 nanoseconds (ns) to 50 ns.

13. The phase change memory according to claim 8, wherein a range of an interval between the at least two consecutive pulses in the first write pulse signal is 5 ns to 15 ns.

14. The phase change memory according to claim 8, wherein the first write pulse signal is a voltage signal comprising at least two consecutive pulses, and an amplitude range of each of the at least two consecutive pulses in the first write pulse signal is 0.5 volt (V) to 1.5 V.