MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
First Claim
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1. A method of bonding a chip to a substrate utilizing at least one multi-layer copper interconnect pillar, comprising:
- providing a chip having a barrier and adhesion layer;
forming a seed layer on the barrier and adhesion layer;
forming a first copper layer directly on and in contact with the seed layer;
forming a first intermediate layer directly on the first copper layer;
forming a second copper layer on first intermediate layer;
forming a second intermediate layer in contact with the second copper layer;
forming a third copper layer in contact with the second intermediate layer; and
bonding the resulting structure to a substrate.
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Abstract
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions
27 Citations
8 Claims
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1. A method of bonding a chip to a substrate utilizing at least one multi-layer copper interconnect pillar, comprising:
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providing a chip having a barrier and adhesion layer; forming a seed layer on the barrier and adhesion layer; forming a first copper layer directly on and in contact with the seed layer; forming a first intermediate layer directly on the first copper layer; forming a second copper layer on first intermediate layer; forming a second intermediate layer in contact with the second copper layer; forming a third copper layer in contact with the second intermediate layer; and bonding the resulting structure to a substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification