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MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME

  • US 20170133338A1
  • Filed: 01/13/2017
  • Published: 05/11/2017
  • Est. Priority Date: 10/11/2007
  • Status: Active Grant
First Claim
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1. A method of bonding a chip to a substrate utilizing at least one multi-layer copper interconnect pillar, comprising:

  • providing a chip having a barrier and adhesion layer;

    forming a seed layer on the barrier and adhesion layer;

    forming a first copper layer directly on and in contact with the seed layer;

    forming a first intermediate layer directly on the first copper layer;

    forming a second copper layer on first intermediate layer;

    forming a second intermediate layer in contact with the second copper layer;

    forming a third copper layer in contact with the second intermediate layer; and

    bonding the resulting structure to a substrate.

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