TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE

• US 20170133377A1
• Filed: 03/24/2014
• Published: 05/11/2017
• Est. Priority Date: 03/24/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: GLASS, Glenn A., MURTHY, Anand S.
• Granted Patent: US 10,141,311 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Claims

1. An integrated circuit comprising:

a first set of fins formed on and from a substrate, the first set of fins each having source/drain regions and a channel region, wherein the first set of fins each have a first width (W1) in the source/drain regions and a second width (W2) in the channel region, and wherein W2 is less than W1; and

a second set of fins formed on and from the substrate, the second set of fins each having source/drain regions and a channel region, wherein the second set of fins each have a third width (W3) in the source/drain regions and the channel region.

2. The integrated circuit of claim 1, wherein:

at least one of the fins in the first or second sets has a first channel height at a first location on the fin and a second channel height at a second location on the fin; and

/or

at least one of the fins in the first set has a first channel height and one of the fins in the second set has a second channel height;

wherein the first and second channel heights comprise intentionally different channel heights.

3. The integrated circuit of claim 1, wherein W1 is greater than 15 nm and W2 is 15 nm or less.

4. The integrated circuit of claim 1, wherein W1 is between 2 nm and 6 nm greater than W2.

5. The integrated circuit of claim 1, wherein W3 is substantially similar to W1.

6. The integrated circuit of claim 1, wherein the first set of fins and the second set of fins each have at least one semiconductor device built thereon.

7. The integrated circuit of claim 6, wherein the semiconductor devices are p-MOS, n-MOS, or CMOS transistor devices.

8. The integrated circuit of claim 1, further comprising a third set of fins formed on and from the substrate, the third set of fins each having source/drain regions and a channel region, wherein the third set of fins each have as fourth width (W4) in the source/drain regions and a fifth width (W5) in the channel region.

9. The integrated circuit of claim 1, wherein W5 is not equal to W2.

10. The integrated circuit of claim 1, wherein the integrated circuit is a system-on-chip (SOC) device.

11. A method of fanning an integrated circuit, the method comprising:

performing a trench etch to form fins and trenches in a substrate, wherein each fin has a first width (W1);

depositing an insulator material in the trenches;

forming dummy gates on channel regions of the fins;

depositing an additional insulator layer over topography of the fins and dummy gates;

lithographically defining a first area to be opened;

removing the dummy gate in the first area to re-expose the channel region of the fins in the first area; and

performing a first trim etch on the channel region of the fins in the first area, wherein the trimmed channel region of each fin in the first area has a second width (W2), and wherein W2 is less than W1.

12. The method of claim 11, further comprising repeating the processes of lithographically defining an area to be opened, removing the dummy gate in that area to re-expose the channel region of the fins in that area, and performing a trim etch on the channel region of the fins in that area to achieve fins having channel regions of varying dimensions.

13. The method of claim 11, further comprising:

lithographically defining a second area to be opened;

removing the dummy gate in the second area to re-expose the channel region of the fins in the second area; and

performing a second trim etch on the channel region of the fins in the second area, wherein the trimmed channel region of each fin in the second area has a third width (W3), and wherein W3 is less than W1.

14. The method of claim 11, wherein lithographically defining comprises forming a hardmask layer and patterning the area to be opened.

15. The method of claim 11, wherein performing a trim etch comprises at least one of low ion energy plasma processing using chlorine based chemistry and thermal processing.

16. The method of claim 11, wherein performing a trim etch comprises using chlorine based chemistry and using less than 5 kW of radio frequency energy for between 10 and 40 seconds.

17. The method of claim 11, wherein performing a trim etch comprises using thermal processing and using less than 900 degrees C. heat in an epitaxial reactor for between 20 and 120 seconds in the presence of HCl.

18. The method of claim 11, wherein performing a trim etch comprises using thermal processing and using less than 700 degrees C. heat in an epitaxial reactor for between 20 and 120 seconds in the presence of Cl₂.

19. The method of claim 11, wherein W1 is greater than 15 nm and W2 is 15 nm or less.

20. The method of claim 11, wherein W3 is not equal to W2.

21. An integrated circuit comprising:

a first set of one or more transistors including finned channel regions formed on and from a substrate; and

a second set of one or more transistors including finned channel regions formed on and from the substrate;

wherein, above isolation regions, at least one of the height and width dimensions of the first set of channel regions is different than the corresponding dimension of the second set of channel regions.

22. The integrated circuit of claim 21, wherein the first set of channel regions has a first width (W1) within isolation regions and a second width (W2) above the isolation regions, and W2 is less than W1.

23. The integrated circuit of claim 21, wherein, above isolation regions, the width of the first set of channel regions is less than the width of the second set of channel regions.

24. The integrated circuit of claim 21, wherein, above isolation regions, the height of the first set of channel regions is less than the width of the second set of channel regions.

25. The integrated circuit of claim 21, wherein, above isolation regions, the width and height of the first set of channel regions is less than the width and height, respectively, of the second set of channel regions.