METHOD OF TREATING A MICROELECTRONIC SUBSTRATE USING DILUTE TMAH

• US 20170141005A1
• Filed: 11/14/2016
• Published: 05/18/2017
• Est. Priority Date: 11/14/2015
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Printz, Wallace P., Rotondaro, Antonio Luis Pacheco, Takahashi, Shuhei, Okamura, Naoyuki, Bassett, Derek W., Yamashita, Masami
• Granted Patent: US 10,256,163 B2
• Time in Patent Office: Days
• CPC Class Codes: C09K 13/00 Etching, surface-brightening or pickling compositions for glass C03C15/00, C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338 ; for metallic material C23F, C23G1/00, C25F1/00; for semi-conductors H01L
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G

Abstract

Embodiments of the invention provide a method for treating a microelectronic substrate with dilute TMAH. In the method, a microelectronic substrate is received into a process chamber, the microelectronic substrate having a layer, feature or structure of silicon. A treatment solution is applied to the microelectronic substrate to etch the silicon, where the treatment solution includes a dilution solution and TMAH. A controlled oxygen content is provided in the treatment solution or in an environment in the process chamber to achieve a target etch selectivity of the silicon, or a target etch uniformity across the layer, feature or structure of silicon, or both by the treatment solution.

Claims

1. A method for treating a microelectronic substrate, comprising:

receiving a microelectronic substrate into a process chamber, the microelectronic substrate comprising a layer, feature or structure of silicon;

applying a treatment solution to the microelectronic substrate to etch the silicon, the treatment solution comprising a dilution solution and TMAH; and

providing a controlled oxygen content in the treatment solution or in an environment in the process chamber to achieve a target etch selectivity of the silicon, or a target etch uniformity across the layer, feature or structure of silicon, or both by the treatment solution.

2. The method of claim 1, further comprising maintaining the treatment solution at a temperature between 20°

C. and 70°

C.

3. The method of claim 1, wherein the dilution solution comprises water or deionized water.

4. The method of claim 3, wherein the dilution solution further comprises hydrogen peroxide or ozone to provide the controlled oxygen content in the treatment solution.

5. The method of claim 4, wherein the dilution solution comprises a concentration of less than 1% by weight of the hydrogen peroxide or ozone.

6. The method of claim 4, wherein the dilution solution comprises a concentration between 0.3% and 0.0001% by weight of the hydrogen peroxide or ozone.

7. The method of claim 4, wherein the dilution solution comprises a concentration between 1 part per billion and 10 parts per million of the hydrogen peroxide or ozone.

8. The method of claim 1, wherein the treatment solution comprises between 20% and 30% by weight of TMAH.

9. The method of claim 1, wherein the treatment solution comprises between 0.1% and 5% by weight of TMAH.

10. The method of claim 1, wherein the layer, feature or structure of silicon comprises a polysilicon feature or structure.

11. The method of claim 10, wherein the layer, feature or structure of silicon comprises a 3DNAND structure or pattern.

12. The method of claim 11 wherein the 3DNAND structure or pattern comprises a longitudinal dimension to lateral dimension aspect ratio of 10:

1 or greater.

13. The method of claim 12, wherein the lateral dimension is between 50 nm and 100 nm and the longitudinal dimension is between 1000 nm and 2000 nm.

14. The method of claim 1, wherein the layer, feature or structure of silicon comprises a copper via structure or pattern formed therein.

15. The method of claim 14, wherein the copper via structure or pattern is a Through-Silicon-Via feature comprising an aspect ratio of 10:

1 or greater.

16. The method of claim 1, wherein the layer, feature or structure of silicon comprises a microbump structure or pattern.

17. The method of claim 1, further comprising exposing the microelectronic substrate to a gas comprising an oxygen concentration of less than 20% during the treatment to provide the controlled oxygen content in the environment in the process chamber.

18. The method of claim 17, wherein the gas is a nitrogen-containing gas comprising a greater amount by weight of nitrogen than oxygen.

19. The method of claim 17, wherein the gas comprises an oxygen concentration less than 5%.

20. The method of claim 17, wherein the gas comprises an oxygen concentration between 1 part per billion and 10 ppm.

21. The method of claim 17, further comprising, after exposing the microelectronic substrate to the treatment solution and the gas and prior to providing a subsequent microelectronic substrate for exposing to the treatment solution and gas, measuring a thickness or profile of the etched layer, feature or structure of silicon and adjusting the controlled oxygen content, temperature of the treatment solution, relative nitrogen to oxygen concentration in the gas or treatment liquid, or pressure of the gas or treatment liquid, or any combination thereof, for the exposing of the subsequent microelectronic substrate to the treatment solution and gas.

22. The method of claim 1, further comprising exposing the treatment solution to a carrier gas comprising an oxygen concentration of less than 20%, prior to applying the treatment solution to the microelectronic substrate to provide the controlled oxygen content in the treatment solution.

23. The method of claim 1, further comprising exposing the substrate to a pre-treatment solution containing hydrofluoric acid, prior to applying the treatment solution to the microelectronic substrate.

24. The method of claim 1 wherein the treatment solution is a mixture of the dilution solution and TMAH, the mixture comprising an oxygen concentration of less than 1% by weight.

25. The method of claim 24, wherein the dilution solution comprises at least one of water or deionized water, and at least one of hydrogen peroxide or ozone.

26. The method of claim 24, wherein the mixture comprises an oxygen concentration less than 1500 ppb.

27. A method for treating a microelectronic substrate, comprising:

receiving a microelectronic substrate into a process chamber, the microelectronic substrate comprising a layer, feature or structure of silicon;

applying a treatment solution to the microelectronic substrate to etch the silicon, the treatment solution comprising a mixture of a dilution solution and TMAH and having a first oxygen concentration of less than 1% by weight;

prior to or during applying the treatment solution, exposing the treatment solution or an environment in the process chamber to a nitrogen-containing gas comprising a second oxygen concentration of less than 20% and a nitrogen concentration greater than the oxygen concentration, wherein the first and second oxygen concentrations are controlled to achieve a target etch selectivity of the silicon, or a target etch uniformity across the layer, feature or structure of silicon, or both by the treatment solution.

28. The method of claim 27, wherein the dilution solution comprises at least one of water or deionized water, and at least one of hydrogen peroxide or ozone.

29. The method of claim 28, wherein the dilution solution comprises a concentration between 0.3% and 0.0001% by weight of the hydrogen peroxide or ozone.

30. The method of claim 28, wherein the layer, feature or structure of silicon comprises a 3DNAND structure or pattern having a longitudinal dimension to lateral dimension aspect ratio of 10:

1 or greater.

31. The method of claim 27, wherein the treatment solution comprises an oxygen concentration less than 1500 ppb and the nitrogen-containing gas comprises an oxygen concentration less than 5%.

32. The method of claim 27, further comprising, after exposing the microelectronic substrate to the treatment solution and the nitrogen-containing gas and prior to providing a subsequent microelectronic substrate for exposing to the treatment solution and nitrogen-containing gas, measuring a thickness or profile of the etched layer, feature or structure of silicon and adjusting one or more of the first oxygen concentration, the second oxygen concentration, temperature of the treatment solution, the nitrogen concentration, or pressure of the nitrogen-containing gas or treatment liquid, or any combination thereof, for the exposing of the subsequent microelectronic substrate to the treatment solution and gas.