SEMICONDUCTOR DEVICE

• US 20170148925A1
• Filed: 02/02/2017
• Published: 05/25/2017
• Est. Priority Date: 09/29/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: NONAKA, Yusuke, YAMAZAKI, Shunpei, HONDA, Tatsuya, TSUBUKU, Masashi, SHIMAZU, Takashi
• Granted Patent: US 10,290,744 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

Claims

1. (canceled)

2. A semiconductor device comprising:

an oxide semiconductor film over a substrate;

a source electrode and a drain electrode electrically connected to the oxide semiconductor film;

a gate electrode; and

a gate insulating film between the gate electrode and the oxide semiconductor film,

wherein the oxide semiconductor film comprises a region in which a concentration of carbon is lower than or equal to 1.0×

10¹⁹ atoms/cm³, and

wherein the region is located at an interface between the oxide semiconductor film and the gate insulating film and in contact with the gate insulating film.

3. The semiconductor device according to claim 2,

wherein the gate insulating film is located over the oxide semiconductor film, and

wherein the gate insulating film comprises an oxide containing silicon.

4. The semiconductor device according to claim 2, wherein an end portion of the oxide semiconductor film is tapered at an angle of 20°

to 50°

.

5. The semiconductor device according to claim 2, further comprising an interlayer insulating film over the gate insulating film and the gate electrode.

6. The semiconductor device according to claim 2, wherein the oxide semiconductor film comprises a crystal portion in which a c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor film.

7. A semiconductor device comprising:

an oxide semiconductor film over a substrate;

a source electrode and a drain electrode electrically connected to the oxide semiconductor film;

a gate electrode; and

a gate insulating film between the gate electrode and the oxide semiconductor film,

wherein the oxide semiconductor film comprises a first region in which a concentration of carbon is lower than or equal to 1.0×

10¹⁹ atoms/cm³, and

wherein the oxide semiconductor film comprises a second region in which a concentration of carbon is lower than the concentration of carbon in the first region.

8. The semiconductor device according to claim 7,

wherein the first region is located at an interface between the oxide semiconductor film and the gate insulating film and in contact with the gate insulating film.

9. The semiconductor device according to claim 7,

wherein the gate insulating film is located over the oxide semiconductor film, and

wherein the gate insulating film comprises an oxide containing silicon.

10. The semiconductor device according to claim 7, wherein an end portion of the oxide semiconductor film is tapered at an angle of 20°

to 50°

.

11. The semiconductor device according to claim 7, further comprising an interlayer insulating film over the gate insulating film and the gate electrode.

12. The semiconductor device according to claim 7, wherein the oxide semiconductor film comprises a crystal portion in which a c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor film.

13. A semiconductor device comprising:

an oxide semiconductor film over a substrate;

a source electrode and a drain electrode electrically connected to the oxide semiconductor film;

a gate electrode; and

a gate insulating film between the gate electrode and the oxide semiconductor film,

wherein the oxide semiconductor film comprises a region in which a concentration of silicon is lower than or equal to 0.1 at. %, and

wherein the region is located at an interface between the oxide semiconductor film and the gate insulating film and in contact with the gate insulating film.

14. The semiconductor device according to claim 13,

wherein the gate insulating film is located over the oxide semiconductor film, and

wherein the gate insulating film comprises an oxide containing silicon.

15. The semiconductor device according to claim 13, wherein an end portion of the oxide semiconductor film is tapered at an angle of 20°

to 50°

.

16. The semiconductor device according to claim 13, further comprising an interlayer insulating film over the gate insulating film and the gate electrode.

17. The semiconductor device according to claim 13, wherein the oxide semiconductor film comprises a crystal portion in which a c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor film.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor film over a substrate; and

forming a source electrode and a drain electrode over the oxide semiconductor film,

wherein the oxide semiconductor film comprises a first region in which a concentration of carbon is lower than or equal to 1.0×

10¹⁹ atoms/cm³, and

wherein the oxide semiconductor film comprises a second region in which a concentration of carbon is lower than the concentration of carbon in the first region.

19. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of:

forming a gate insulating film over the oxide semiconductor film; and

forming a gate electrode over the gate insulating film,

wherein the gate insulating film comprises an oxide containing silicon.