Accessing Data Via Different Clocks

• US 20170155497A1
• Filed: 12/01/2015
• Published: 06/01/2017
• Est. Priority Date: 12/01/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Barrenscheen, Jens
• Granted Patent: US 10,447,461 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An example relates to a method for accessing data of a first domain that is driven by a first clock via a second clock, comprising at least one of the following: accessing the data of the first domain via the second clock during a time when the first clock is in a first logical state. An edge indicating a transition from a second logical state to the first logical is used to access data via the first clock, or accessing the data of the first domain via the second clock at edges of the first clock that are synchronized with edges of the second clock.

Claims

1. A method comprising:

accessing data of a first domain that is driven by a first clock via a second clock;

wherein the access to the data occurs with a defined phase-relation between the first clock and the second clock.

2. The method according to claim 1, wherein the first clock is asynchronous to the second clock.

3. The method according to claim 1, wherein the first clock has a lower frequency than the second clock.

4. The method according to claim 3,

wherein the first clock has a first periodic time and the second clock has a second periodic time;

wherein the first periodic time comprises first time interval of a first logical level and second time interval of a second logical level;

wherein the first time interval is larger than the second periodic time; and

wherein the second time interval is larger than the second periodic time of the second clock.

5. The method according to claim 1, wherein the second clock determines an access to data of a second domain or a fast access to data of the first domain.

6. The method according to claim 1, wherein the first clock is enabled while the second clock is disabled.

7. The method according to claim 1, wherein the first domain comprises a processing unit driven by the first clock and a memory that is accessible to the processing unit.

8. The method according to claim 7, wherein a second domain comprises a second processing unit driven by the second clock, the second processing unit being arranged to access the memory of the first domain.

9. The method according to claim 7, wherein the data of the first domain are stored within the memory.

10. The method according to claim 1, wherein the first clock is used for accessing the data of the first domain in case the second clock is switched off.

11. The method according to claim 1, wherein, based on the first clock, a cycle of the second clock is determined, wherein the cycle of the second clock is used for accessing the data of the first domain.

12. The method according to claim 11, wherein an edge of the first clock or a level of the first clock is used for selecting an edge of the second clock.

13. The method according to claim 12, wherein the edge is a rising edge.

14. The method according to claim 1, further comprising accessing the data of the first domain via the second clock during a time when the first clock has changed from a second logical state to a first logical state, wherein the data of the first domain are accessed via the second clock after a predetermined amount of time after the first clock has changed from the second logical state to the first logical state.

15. The method according to claim 14, wherein the first logical state corresponds to logical “

0” and

the second logical state corresponds to logical “

1”

or vice versa.

16. A computer program product directly loadable into a memory of a digital processing device, comprising software code portions for performing the steps of the method according to claim 1.

17. A device comprising:

a first domain comprising first clock circuit configured to generate a first clock signal and a memory configured to store data to be accessed; and

a second domain comprising a second clock circuit configured to generate a second clock signal and a second processing unit, the second processing unit coupled to the memory;

wherein the first clock signal and the second clock signal are set to a defined phase-relation for accessing the data.

18. The device according to claim 17, wherein the first clock signal operates at a lower frequency than the second clock signal.

19. The device according to claim 18,

wherein the first clock signal has a first periodic time and the second clock signal has a second periodic time;

wherein the first periodic time comprises a first time interval of a first logical level and a second time interval of a second logical level;

wherein the first time interval is larger than the second periodic time; and

wherein the second time interval is larger than the second periodic time of the second clock signal.

21. The device according to claim 17, wherein the second processing unit is configured to access the data of the first domain via the second clock signal during a time after the first clock signal has changed from a second logical state to a first logical state;

and

wherein the data of the first domain are accessed via the second clock signal a predetermined amount of time after the first clock signal has changed from the second logical state to the first logical state.

22. The device according to claim 17, wherein the first domain further comprises a first processing unit.

23. The device according to claim 17, wherein the first domain is a standby domain and the second domain is a core domain, wherein the second clock signal operates at a higher frequency than the first clock signal.

24. The device according to claim 17, wherein the first clock signal is enabled while the second clock signal is disabled.

20. The device according to claim 170, wherein the second processing unit is configured to determine a cycle of the second clock signal based on the first clock signal, wherein the cycle of the second clock signal is used for accessing the data in the memory of the first domain.

25. A device for accessing data of a first domain that is driven by a first clock via a second clock, comprising:

a first domain comprising a first clock and a memory for storing the data;

a second domain comprising a second clock and a second processing unit; and

means for setting the first clock and the second clock to a defined phase-relation for accessing the data.