SENSE AMPLIFIER

• US 20170169870A1
• Filed: 02/27/2017
• Published: 06/15/2017
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Dray, Cyrille, Boujamaa, El Mehdi
• Granted Patent: US 10,127,959 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.

Claims

1. A circuit comprising:

a memory cell; and

a sense amplifier circuit coupled to the memory cell, wherein the sense amplifier circuit includes;

a first path including a first intermediate node;

a second path including a second intermediate node, wherein the sense amplifier circuit is to generate a voltage difference between the first and second intermediate nodes that corresponds to a value of a bit stored by the memory cell; and

a latch circuit direct current (DC) coupled between the first and second intermediate nodes, wherein the latch circuit, when activated by an enable signal, is to generate a digital output signal based on the voltage difference between the first and second intermediate nodes.

2. The circuit of claim 1, wherein the latch circuit includes a first enable transistor coupled between pull-up transistors of the latch circuit and a supply terminal and a second enable transistor coupled between pull-down transistors of the latch circuit and a ground terminal, wherein the first and second enable transistors are to turn on responsive to the enable signal to activate the latch circuit after generation of the voltage difference.

3. The circuit of claim 2,

wherein the pull-up transistors include:

a first pull-up transistor having a drain terminal coupled to the first intermediate node and a gate terminal coupled to the second intermediate node; and

a second pull-up transistor having a drain terminal coupled to the second intermediate node and a gate terminal coupled to the first intermediate node; and

wherein the pull-down transistors include;

a first pull-down transistor having a drain terminal coupled to the first intermediate node and a gate terminal coupled to the second intermediate node; and

a second pull-down transistor having a drain terminal coupled to the second intermediate node and a gate terminal coupled to the first intermediate node.

4. The circuit of claim 1, wherein the sense amplifier further includes a cutoff transistor coupled between the first and second paths to turn off responsive to activation of the latch circuit.

5. The circuit of claim 4, wherein the sense amplifier further includes:

a first feedback transistor with a drain terminal coupled to a drain terminal of the cutoff transistor and a gate terminal coupled to the first intermediate node; and

a second feedback transistor with a drain terminal coupled to a source terminal of the cutoff transistor and a gate terminal coupled to the second intermediate node.

6. The circuit of claim 4, wherein the sense amplifier further includes:

first output logic coupled to the first intermediate node to selectively pass a first digital value based on the voltage at the first intermediate node responsive to the enable signal;

second output logic coupled to the second intermediate node to selectively pass a second digital value based on the voltage at the second intermediate node responsive to the enable signal, wherein the second digital value is the inverse of the first digital value; and

cutoff logic to receive the first and second digital values as inputs and having an output terminal coupled to a gate terminal cutoff transistor to turn off the cutoff transistor responsive to receipt of the first and second digital values.

7. A memory system comprising:

a resistive memory including a resistive memory cell;

a reference cell having a first resistance;

a sense amplifier coupled to the resistive memory cell and the reference cell, the sense amplifier to read data from the resistive memory cell based on the reference cell;

a first trimmable resistor coupled between the sense amplifier and the resistive memory cell;

a second trimmable resistor coupled between the sense amplifier and the reference cell; and

a control circuit to adjust resistance values of the first trimmable resistor and the second trimmable resistor to equalize read margins between a logic 0 read and a logic 1 read of the memory cell.

8. The system of claim 7, wherein the reference cell is a first reference cell, wherein the system further comprises:

a second reference cell with a second resistance that is different from the first resistance;

a third trimmable resistor coupled between the sense amplifier and the second reference cell;

wherein the sense amplifier is to read the data from the resistive memory cell based on the first and second reference cells; and

wherein the control circuit is to adjust a resistance value of the third trimmable resistor to equalize the read margins.

9. The system of claim 8, wherein the control circuit is to control the second and third trimmable resistors to have the same resistance value.

10. The system of claim 8, wherein the sense amplifier includes:

a first path including a first intermediate node;

a second path including a second intermediate node; and

switch circuitry to;

during a first phase of the read, couple the first reference cell to the first path and couple the resistive memory cell to the second path; and

during a second phase of the read, couple the resistive memory cell to the first path and couple the second reference cell to the second path to generate a voltage difference between the first and second intermediate nodes that corresponds to a value of a bit stored by the resistive memory cell.

11. An apparatus comprising:

means to, during a first phase of a read operation, couple a reference cell to a first path and couple a memory cell to a second path;

means to, during a second phase of the read operation, couple the memory cell with the first path to generate a voltage difference between a first intermediate node on the first path and a second intermediate node on the second path that corresponds to a value of a bit stored by the memory cell; and

means to generate a bias voltage to control a first transistor of the first path to provide a voltage across the memory cell or reference cell and induce a current in the first path, the bias voltage having a value based on a threshold voltage of a second transistor.

12. The apparatus of claim 11, wherein the means to generate the bias voltage is to copy a current on the first path and pass the copied current through the second transistor to generate the bias voltage.

13. The apparatus of claim 11, further comprising means to adjust an offset resistance associated with the memory cell or the reference cell to balance read margins of the read operation.

14. The apparatus of claim 11, further comprising means to generate a digital output signal based on the generated voltage difference between the first and second intermediate nodes, wherein the means to generate the digital output signal are direct current (DC) coupled to the first and second intermediate nodes.