Method of Semiconductor Integrated Circuit Fabrication

• US 20170170066A1
• Filed: 02/13/2017
• Published: 06/15/2017
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Ching-Fu, Peng, Chao-Hsien, Wu, Hsien-Chang, Lee, Hsiang-Huan
• Granted Patent: US 9,947,583 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Claims

1. A method comprising:

forming a conductive layer on a substrate;

forming a catalyst layer on the conductive layer;

forming a plurality of carbon nanotubes (CNTSs) from the catalyst layer; and

patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features.

2. The method of claim 1, further comprising forming a dielectric layer directly on the plurality of CNTs.

3. The method of claim 1, further comprising forming a patterned material layer over the conductive layer, the patterned material layer defining an opening, and

wherein forming the catalyst layer on the conductive layer includes forming the catalyst layer in the opening defined by the patterned material layer.

4. The method of claim 3, wherein the patterned material layer includes a photoresist material.

5. The method of claim 3, further comprising removing the patterned material layer prior to forming the plurality of CNTSs from the catalyst layer.

6. The method of claim 1, further comprising forming a patterned hard mask layer over the conductive layer, and

wherein patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features includes patterning the conductive layer by using the patterned hard mask layer as a mask.

7. The method of claim 1, wherein forming the catalyst layer on the conductive layer includes forming the catalyst layer directly on the conductive layer such that the catalyst layer physically contacts the conductive layer.

8. A method comprising:

forming a conductive layer on a substrate;

forming a patterned material layer on the conductive layer, the patterned material layer defining an opening that exposes a portion of the conductive layer;

forming a catalyst layer on the exposed portion of the conductive layer;

removing the patterned material layer;

forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features.

9. The method of claim 8, further comprising forming a patterned hard mask layer on the conductive layer prior to forming the patterned material layer on the conductive layer.

10. The method of claim 9, wherein forming the patterned material layer on the conductive layer includes forming the patterned material layer directly on the patterned hard mask layer.

11. The method of claim 10, wherein the patterned hard mask layer defines another opening, and

wherein forming the patterned material layer on the conductive layer includes forming the patterned material layer within the another opening.

12. The method of claim 8, wherein removing the patterned material layer occurs prior to forming the plurality of CNTs from the catalyst layer.

13. The method of claim 8, wherein patterning the conductive layer by using CNTs as the mask to form conductive features includes performing a dry etch process.

14. The method of claim 8, further comprising forming a dielectric layer directly on the conductive features and the plurality of CNTs.

15. A method comprising:

forming a metal layer on a substrate;

forming a patterned first material layer on the metal layer, the patterned first material layer defining an opening that exposes a portion of the metal layer;

forming a patterned second material layer on the patterned first material layer and within the opening;

forming a catalyst layer on the exposed portion of the metal layer;

removing the patterned second material layer;

forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

etching the metal layer by using the plurality of CNTs as a mask.

16. The method of claim 15, wherein the patterned first material layer is formed of a different material than the patterned second material layer.

17. The method of claim 15, wherein removing the patterned second material layer exposes the portion of the metal layer.

18. The method of claim 15, wherein forming the patterned first material layer on the metal layer includes forming the patterned first material layer directly on the metal layer such that the patterned first material layer physically contacts the metal layer,

wherein forming the patterned second material layer on the patterned first material layer includes forming the patterned second material layer directly on the patterned first material layer such that the patterned second material layer physically contacts the patterned first material layer, and

wherein forming the catalyst layer on the exposed portion of the metal layer includes forming the catalyst layer directly on the exposed portion of the metal layer such that the catalyst layer physically contacts the exposed portion of the metal layer.

19. The method of claim 15, wherein etching the metal layer by using the plurality of CNTs as a mask includes etching the metal layer by using the patterned first material layer as a mask.

20. The method of claim 15, wherein etching the metal layer by using the plurality of CNTs as the mask exposes a portion of the substrate.