WIRE BOND FREE WAFER LEVEL LED

• US 20170179088A1
• Filed: 03/03/2017
• Published: 06/22/2017
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ibbetson, James, Medendorp, JR., Nicholas W., Chitnis, Ashay, Keller, Bernd, Batres, Max
• Granted Patent: US 10,199,360 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

Claims

1. A device comprising:

a plurality of active regions, each of which is between an n-type layer and a p-type layer, wherein one of said n-type or p-type layers comprises the primary emission surface;

one or more n-electrodes and corresponding one or more vias; and

one or more p-electrodes, wherein said n-electrodes and p-electrodes are in electrical contact with said active regions, and wherein said n-electrodes and p-electrodes are on the side of said active region opposite said primary emission surface.

2. The device of claim 1, comprising a single n-type layer and a plurality of p-type layers, wherein each of said active regions are between said single n-type layer and a respective one of said plurality of p-type layers.

3. The device of claim 2, wherein said n-type layer comprises the primary emission surface, and said n-electrodes contacting said n-type layer between said active regions.

4. The device of claim 2, wherein said n-electrodes contact said n-type layer between said p-type layers.

5. The device of claim 1, wherein each of said one or more n-electrodes is in electrical contact with said n-type layer.

6. The device of claim 1, comprising a plurality of p-type layers wherein each of said p-electrodes is in contact with a respective one of said p-type layers.

7. The device of claim 1, further comprising a plurality of spacer elements coupled to the n-electrode and the p-electrode, such that each of said spacer elements electrically isolates one of said n-electrodes from one of said p-electrodes.

8. The device of claim 7, wherein each of said n-electrodes and said p-electrodes extend laterally over at least one of said spacer elements.

9. The device of claim 1, further comprising a wavelength conversion layer adjacent said primary emission surface.

10. The device of claim 1, wherein said n-electrodes and said p-electrodes have surfaces that are coplanar.

18. The device of claim 7, wherein each of said n-electrodes and said p-electrodes extend laterally over at least one of said spacer elements.

19. The device of claim 1, further comprising one or more wavelength conversion layers adjacent said active regions.

11. A device comprising:

a plurality of active regions each having a primary emission surface;

multiple n-electrodes accessible from a surface opposite the primary emission surface and each providing an electrical path to one or more of said active regions; and

multiple p-electrodes on the same side of said active regions as said n-electrodes, each of said p-electrodes also accessible from a surface opposite the primary emission surface and providing an electrical path to one or more of said active regions, wherein said n-electrodes and said p-electrodes have surfaces that are coplanar.

12. A device of claim 11, wherein each of said active regions is between a respective one of a plurality of n-type layers and a respective one of plurality of p-type layers.

13. The device of claim 12, wherein each of said p-type layers is each of said active regions primary emission surface.

14. The device of claim 12, wherein each of said n-type layers is each of said active regions primary emission surface.

15. The device of claim 11, wherein each of said active regions comprises a flip-chip light emitting diode (LED) structure.

16. The device of claim 12, wherein each of said multiple n-electrodes is in electrical contact with one of said n-type layers and each of said p-electrodes is in contact with a respective one of said p-type layers.

17. The device of claim 11, further comprising a plurality of spacer elements each of which electrically isolates one of said n-electrodes from one of said p-electrodes.

20. A device comprising:

a plurality of active regions each having a primary emission surface;

multiple n-electrodes accessible from a surface opposite the primary emission surface and each providing an electrical path to one or more of said active regions; and

multiple p-electrodes on the same side of said active regions as said n-electrodes, each of said p-electrodes also accessible from a surface opposite the primary emission surface and providing an electrical path to one or more of said active regions, wherein said n-electrodes and said p-electrodes provide primary mechanical support for said device.