MEMORY SYSTEM

• US 20170192706A1
• Filed: 01/05/2015
• Published: 07/06/2017
• Est. Priority Date: 05/13/2014
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJIMOTO, Akihisa, SAKAMOTO, Hiroyuki
• Granted Patent: US 10,558,378 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

According to one embodiment, there is provided a memory system including a power supply terminal, a plurality of couplers, and a control unit. The power supply terminal is a terminal to be connected to a power supply line of a host. The plurality of couplers are couplers to be electromagnetically coupled respectively to couplers of the host. The control unit can establish a reception channel and a transmission channel that are independent of each other between the memory system and the host via the plurality of couplers according to level of a power supply voltage supplied from the host via the power supply line and the power supply terminal.

Claims

1. A memory system comprising:

a power supply terminal to be connected to a power supply line of a host;

a plurality of couplers to be electromagnetically coupled respectively to couplers of the host; and

a control unit that can establish a reception channel and a transmission channel that are independent of each other between the memory system and the host via the plurality of couplers according to level of a power supply voltage supplied from the host via the power supply line and the power supply terminal.

2. The memory system according to claim 1, wherein

each of the plurality of couplers has directivity.

3. The memory system according to claim 1, wherein

the plurality of couplers form a plurality of communication channels having different frequency bands from each other.

4. The memory system according to claim 1, wherein

the plurality of couplers are placed away from each other at a predetermined short distance or greater.

5. The memory system according to claim 1, wherein

the control unit, in response to the level of the power supply voltage supplied from the host being switched from a first level to a second level higher than the first level, sequentially receives host basic information about capabilities of the host and test symbols from the host via a first communication channel from among the plurality of communication channels, transmits memory-system basic information about capabilities of the memory system to the host via a second communication channel from among the plurality of communication channels while receiving the test symbols via the first communication channel, and sets the first communication channel as a reception channel and the second communication channel as a transmission channel.

6. The memory system according to claim 5, wherein

in a case where the host can correctly receive the memory-system basic information while the test symbols is being received via the first communication channel, the control unit sets the first communication channel as a reception channel in overlap-type full-duplex communication and the second communication channel as a transmission channel in the overlap-type full-duplex communication.

7. The memory system according to claim 5, wherein

in response to the host not having been able to correctly receive the memory-system basic information while the test symbols were being received via the first communication channel, the control unit receives the host basic information from the host via the first communication channel, transmits the memory-system basic information to the host via the second communication channel while the test symbols do not exist on the first communication channel, and sets, in a case where the host can correctly receive the memory-system basic information while the test symbols do not exist on the first communication channel, the first communication channel as a reception channel in non-overlap-type full-duplex communication and the second communication channel as a transmission channel in the non-overlap-type full-duplex communication.

8. The memory system according to claim 7, wherein

in a case where the host cannot correctly receive the memory-system basic information while the test symbols do not exist on the first communication channel, the control unit sets one of the first communication channel and the second communication channel as a transmission/reception dual-purpose channel in half-duplex communication.

9. The memory system according to claim 5, wherein

in a case where the memory system receives a request to switch to an extended mode adopted by the host from among capabilities included in the memory-system basic information from the host via the first communication channel, if the memory system can accept switching to the extended mode, the control unit transmits response information indicating acceptance to the host via the second communication channel.

10. The memory system according to claim 9, wherein

in response to the level of the power supply voltage supplied from the host being switched from the second level to a third level between the first level and the second level back to the second level again, the control unit has communication operation of the memory system go into an extended mode agreeing with capability list and establishes the first communication channel as a reception channel agreeing with the extended mode and the second communication channel as a transmission channel agreeing with the extended mode.

11. The memory system according to claim 10, wherein

after establishing the reception channel and the transmission channel, in response to the level of the power supply voltage supplied from the host via the power supply terminal being switched from the second level to the third level, the control unit has communication operation of the memory system go from the extended mode into a power saving mode.

12. The memory system according to claim 11, wherein

in response to the level of the power supply voltage supplied from the host via the power supply terminal returning from the third level to the second level, the control unit has communication operation of the memory system return from the power saving mode to the extended mode.

13. The memory system according to claim 11, wherein

while the level of the power supply voltage supplied from the host via the power supply terminal is the third level, the control unit transmits a trigger signal to request to switch the level of the power supply voltage back to the second level to the host via the second communication channel, and, in response to the level of the power supply voltage supplied from the host via the power supply terminal returning from the third level to the second level in response to the trigger signal, stops transmitting the trigger signal and has communication operation of the memory system return from the power saving mode to the extended mode.

14. The memory system according to claim 1, wherein

the control unit has:

a voltage recognizer that recognizes the level of the power supply voltage supplied from the host via the power supply terminal using a first reference level and a second reference level higher than the first reference level;

a first regulator that, in a case where the level of the power supply voltage supplied is greater than or equal to the first reference level, generates a first internal voltage and, in a case where the level of the power supply voltage supplied is less than the first reference level, stops operating;

a second regulator that, in a case where the level of the power supply voltage supplied is greater than or equal to the second reference level, generates a second internal voltage higher than the first internal voltage and, in a case where the level of the power supply voltage supplied is less than the second reference level, stops operating;

a first internal circuit that, in a case where the level of the power supply voltage supplied is greater than or equal to the first reference level, operates with use of the first internal voltage; and

a second internal circuit that, in a case where the level of the power supply voltage supplied is greater than or equal to the second reference level, operates with use of the second internal voltage and, in a case where the level of the power supply voltage supplied is less than the second reference level, suspends operation.

15. The memory system according to claim 14, wherein

the first internal circuit includes a circuit that performs control to establish a communication channel, or registers or a memory to hold states while power is being saved.

16. The memory system according to claim 1, wherein

the memory system is a memory card to be inserted into the host and comprises a plurality of the power supply terminals, and

the plurality of power supply terminals are arranged rotationally symmetrical with respect to an insertion direction of the memory system, and

wherein the plurality of couplers are arranged rotationally symmetrical with respect to the insertion direction of the memory system, and

the memory system has a mechanism that determines pairs of a coupler of the memory system and a coupler of the host.

17. The memory system according to claim 16, wherein

the memory system further comprises a plurality of ground terminals to be respectively connected to ground lines of the host, and the plurality of ground terminals are arranged rotationally symmetrical with respect to the insertion direction of the memory system.

18. The memory system according to claim 1, wherein

the host has a shield structure to shield the plurality of couplers electromagnetically, and

the plurality of couplers are electromagnetically coupled to the couplers of the host respectively in a case of being located in a space shielded by the shield structure.

19. The memory system according to claim 18, further comprising:

a second coupler to be electromagnetically coupled to a coupler of a second host and configured so as to be located outside the space shielded by the shield structure in a case where the plurality of couplers are located in the space shielded by the shield structure.

20. The memory system according to claim 19, wherein

each of the plurality of couplers has directivity, and

the second coupler is lessened in directivity than the plurality of couplers.