ARRAY SUBSTRATE, ITS DRIVING METHOD AND MANUFACTURING METHOD, AND DISPLAY DEVICE

• US 20170205953A1
• Filed: 08/10/2016
• Published: 07/20/2017
• Est. Priority Date: 01/14/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: SUN, Chaochao, LIU, Huafeng, ZHAO, Shengwei, YE, Lulu, YANG, Lei, LV, Jingping, HU, Chongliang, YANG, Meng, DING, Duolong, SHUN, Bule, XIE, Lin, LI, Yao, SUN, Shimin, ZHANG, Kai, WANG, Chao
• Granted Patent: US 10,564,772 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 2203/04107 Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: H01L 27/124 : with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 : with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 : Multistep manufacturing methods

Abstract

The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.

Claims

1. An array substrate, comprising a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer,

wherein the first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer comprises a pattern of touch electrodes, and the third transparent conductive layer comprises a pattern of pixel electrodes;

and

within any one of pixel areas of the display area, a corresponding pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.

2. The array substrate according to claim 1, wherein within any one of the pixel areas of the display area, the pixel electrode overlaps the first transparent conductive layer to form a first storage capacitor at the pixel area, and the pixel electrode overlaps a corresponding touch electrode to form a second storage capacitor at the pixel area.

3. The array substrate according to claim 1, wherein the transistor layer comprises an active layer, a gate insulation layer, a gate metal layer, an interlayer medium layer, a source-drain metal layer and a passivation layer formed sequentially, and within any one of the pixel areas of the display area, the passivation layer is provided with an opening so as to expose a portion of the source-drain metal layer, thereby to form the pixel electrode connection end.

4. The array substrate according to claim 1, wherein the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer and the third transparent conductive layer are arranged sequentially on the transistor layer.

5. The array substrate according to claim 1, wherein the first transparent conductive layer and the second transparent conductive layer are each arranged at an area outside an area of the via-hole, and separated from the via-hole.

6. The array substrate according to claim 3, wherein the gate insulation layer and the interlayer medium layer are provided with a via-hole through which the source-drain metal layer is connected to the active layer.

7. The array substrate according to claim 1, wherein the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer and the third transparent conductive layer are each of a thickness within a range from 100 Å

to 5000 Å

.

8. A method for driving the array substrate according to claim 1, comprising steps of:

at a display stage, applying a common voltage to the touch electrode in the second transparent conductive layer and to the first transparent conductive layer; and

at a touch stage, applying a touch voltage signal to the touch electrode in the second transparent conductive layer, or receiving a touch sensing signal from the touch electrode in the second transparent conductive layer,

wherein the display stage is temporally separated from the touch stage within each image frame.

9. The method according to claim 8, further comprising:

at the touch stage, applying the common voltage to the first transparent conductive layer.

10. The method according to claim 8, further comprising:

at the touch stage, setting pixel electrodes in the third transparent conductive layer to be in a floating state.

11. The method according to claim 8, wherein the common voltage is of a value within a range from −

5V to +5V.

16. A display device, comprising the array substrate according to claim 1.

17. The display device according to claim 16, wherein within any one of pixel areas of the display area, the pixel electrode overlaps the first transparent conductive layer to form a first storage capacitor at the pixel area, and the pixel electrode overlaps a corresponding touch electrode to form a second storage capacitor at the pixel area.

18. The display device according to claim 16, wherein the transistor layer comprises an active layer, a gate insulation layer, a gate metal layer, an interlayer medium layer, a source-drain metal layer and a passivation layer formed sequentially, and within any one of the pixel areas of the display area, the passivation layer is provided with an opening so as to expose a portion of the source-drain metal layer, thereby to form the pixel electrode connection end.

19. The display device according to claim 16, wherein the first transparent conductive layer, the first insulation layer, the second transparent conductive layer, the second insulation layer and the third transparent conductive layer are arranged sequentially on the transistor layer.

20. The display device according to claim 18, wherein the gate insulation layer and the interlayer medium layer are provided with a via-hole through which the source-drain metal layer is connected to the active layer.

12. A method for manufacturing an array substrate, comprising steps of:

forming a first transparent conductive layer covering a transistor layer at a display area, the first transparent conductive layer being provided with an opening at a position corresponding to a via-hole for connecting a pixel electrode connection end of the transistor layer;

forming a first insulation layer covering the first transparent conductive layer;

forming on the first insulation layer a second transparent conductive layer including a pattern of touch electrodes;

forming a second insulation layer covering the second transparent conductive layer and the first insulation layer;

forming the via-hole in the first insulation layer and the second insulation layer; and

forming a third transparent conductive layer including a pattern of pixel electrodes, wherein within any one of pixel areas of the display area, a corresponding pixel electrode is connected to the pixel electrode connection end of the transistor layer through the via-hole.

13. The method according to claim 12, wherein within any one of pixel areas of the display area, the pixel electrode overlaps the first transparent conductive layer to form a first storage capacitor at the pixel area, and the pixel electrode overlaps the touch electrode to form a second storage capacitor at the pixel area.

14. The method according to claim 12, further comprising a step of:

prior to the step of forming the first transparent conductive layer covering the transistor layer at the display area, forming the transistor layer on a base.

15. The method according to claim 14, wherein the step of forming the transistor layer on the base comprises sequentially forming an active layer, a gate insulation layer, a gate metal layer, an interlayer medium layer, a source-drain metal layer and a passivation layer, and within any one of the pixel areas of the display area, the passivation layer is provided with an opening so as to expose a portion of the source-drain metal layer, thereby to form the pixel electrode connection end.