Power Management Architecture

• US 20170220100A1
• Filed: 05/31/2016
• Published: 08/03/2017
• Est. Priority Date: 02/02/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: DiBene, II, Joseph T., Hartley, David A., Sodhi, Inder M.
• Granted Patent: US 10,209,767 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Claims

1. An integrated circuit comprising:

a plurality of pipeline stage circuits;

a plurality of voltage regulators integrated into the integrated circuit with the plurality of pipeline circuits, each of the plurality of voltage regulators;

coupled to a respective pipeline stage circuit;

configured to supply a regulated supply voltage to the respective pipeline stage circuit; and

includes one or more energy storage components; and

a plurality of control circuits coupled to the plurality of pipeline stage circuits and the plurality of voltage regulators, wherein;

a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits; and

the given control circuit is configured to cause a given voltage regulator of the plurality of voltage regulators to supply power to the given pipeline stage circuit in response to the activity indicator indicating activity.

2. The integrated circuit as recited in claim 1, wherein given control circuit is further configured to cause a clock to be ungated to the given pipeline stage circuit in response to the expiration of a delay from the power being supplied by the given power supply circuit.

3. The integrated circuit as recited in claim 2, wherein the delay is less than or equal to 5 clock periods of the ungated clock.

4. The integrated circuit as recited in claim 1, wherein:

a first pipeline stage circuit of the plurality of pipeline stage circuits is coupled a first activity indicator;

the first pipeline stage circuit is configured to process data provided to the first pipeline stage circuit to produce output data and a second activity indicator to a second pipeline stage circuit of the plurality of pipeline stage circuits;

a first control circuit of the plurality of control circuits is configured to cause a first voltage regulator of the plurality of voltage regulators to supply power to the first pipeline stage circuit responsive to the first activity indicator;

a second control circuit of the plurality of control circuits is configured to cause a second voltage regulator of the plurality of voltage regulators to supply power to the second pipeline stage circuit responsive to the second activity indicator; and

a first period of time in which power is supplied to the first pipeline stage circuit overlaps with a second period of time in which power is supplied to the second pipeline stage circuit.

5. The integrated circuit as recited in claim 4, wherein:

the first control circuit is configured to generate a third indicator prior to the second activity indicator;

the third indicator indicates that the second activity indicator is to activate; and

the second control circuit is configured to cause the second voltage regulator to supply power responsive to the third indicator prior to assertion of the second activity indicator.

6. The integrated circuit as recited in claim 1 further comprising:

a plurality of clock gater circuits coupled to respective pipeline stage circuits of the plurality of pipeline stage circuits, wherein the plurality of clock gater circuits are configured to ungate clocks to the respective pipeline stage circuits responsive to first enables from the plurality of control circuits.

7. The integrated circuit as recited in claim 1, wherein a first pipeline circuit of the plurality of pipeline stage circuits comprises a plurality of pipeline stages.

8. The integrated circuit as recited in claim 7, wherein a second pipeline circuit of the plurality of pipeline circuits is a single pipeline stage.

9. The integrated circuit as recited in claim 1, wherein:

the plurality of pipeline stage circuits are configured to process image data into pixels;

a data fetch stage is configured to fetch data from memory; and

the activity indication results from the data returning from memory to be processed.

10. The integrated circuit as recited in claim 1, wherein:

the plurality of pipeline stage circuits comprise execution stages of a processor; and

the activity indication indicates an instruction issued to the execution stages.

11. The integrated circuit as recited in claim 1, wherein the plurality of pipeline stage circuits comprise an image signal processor and the activity indication indicates camera data being provided to the image signal processor.

12. The integrated circuit as recited in claim 1, wherein the plurality of pipeline stage circuits comprise a graphics processor and the activity indication indicates vertex data is available for processing.

13. An apparatus comprising:

a plurality of pipeline stage circuits; and

a plurality of control circuits coupled to the plurality of pipeline stage circuits, wherein;

a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits;

the activity indicator indicates whether or not there is activity at an input to the given pipeline stage circuit;

the given control circuit of the plurality of control circuits is coupled to a second indicator that indicates, in advance of the activity indicator, that the activity indicator will be indicating activity; and

the given control circuit and is configured to cause power and clock to be supplied to the given pipeline stage circuit in response to the second indicator; and

a controller circuit coupled to the plurality of control circuits and the plurality of pipeline stage circuits, wherein the controller circuit is configured to generate at least the second indicator for the given pipeline stage circuit.

14. The apparatus as recited in claim 13, wherein:

the given control circuit is configured to generate a third indicator indicating that a second activity indicator that indicates activity to a next pipeline stage circuit in series with the given pipeline circuit will be indicating activity; and

a second control circuit of the plurality of control circuit is configured to cause power and clock to be supplied to the second pipeline stage circuit in response to the third indicator.

15. The apparatus as recited in claim 13 further comprising:

a plurality of voltage regulators, each voltage regulator coupled to a respective pipeline circuit of the plurality of pipeline stage circuits, and each voltage regulator configured to supply power to the respective pipeline stage circuit responsive to an enable from a respective control circuit of the plurality of control circuits.

16. The apparatus as recited in claim 15, wherein each voltage regulator includes one or more energy storage components.

17. The apparatus as recited in claim 13, wherein:

the controller circuit is configured to generate the second indicator in response to monitoring activity in the plurality of pipeline stage circuits.

18. The apparatus as recited in claim 17, wherein the controller is configured to generate the activity indicator in response to monitoring activity in the plurality of pipeline stage circuits.

19. An apparatus comprising:

a plurality of pipeline stage circuits; and

a plurality of control circuits coupled to the plurality of pipeline stage circuits, wherein;

the plurality of control circuits are configured to control the supply of power and clock to the plurality of pipeline stage circuits;

a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits;

the given control circuit is configured to cause power to be supplied to the given pipeline stage circuit in response to the activity indicator indicating activity; and

the given control circuit is configured to cause the clock to be ungated to the given pipeline stage circuit in response to the expiration of a delay from the power being supplied.

20. The apparatus as recited in claim 19, wherein:

a first pipeline stage circuit of the plurality of pipeline stage circuits is coupled to a first activity indicator;

the first pipeline stage circuit is configured to process data provided to the first pipeline stage circuit to produce output data and a second activity indicator to a second pipeline stage circuit of the plurality of pipeline stage circuits;

a first control circuit of the plurality of control circuits is configured to cause power and clock to be supplied to the first pipeline stage circuit responsive to the first activity indicator;

a second control circuit of the plurality of control circuits is configured to cause power and clock to be supplied to the second pipeline stage circuit; and

a first period of time in which power is supplied to the first pipeline stage circuit overlaps with a second period of time in which power is supplied to the second pipeline stage circuit.