SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20170221571A1
• Filed: 07/20/2016
• Published: 08/03/2017
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: JOO, Byoung In
• Granted Patent: US 10,388,332 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Claims

1. A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:

receiving a request for performing a target operation from a controller configured to control the semiconductor memory device;

generating a synchronizing signal for performing the target operation; and

detecting temperatures of memory cells included in the semiconductor memory device in response to the synchronizing signal.

2. The method of claim 1, wherein the synchronizing signal is an operation end pulse generated as the target operation is completed.

3. The method of claim 2, wherein, when the target operation is a program or erase operation, the operation end pulse is generated when a pass or a fail of the program or erase operation is determined.

4. The method of claim 2, wherein, when the target operation is a read operation, the operation end pulse is generated when fail of the read operation is determined or when data read in accordance with the read operation is stored.

5. The method of claim 1, wherein the target operation includes at least one of a program related operation, a read related operation, and an erase related operation for the plurality of memory cells.

6. The method of claim 1, wherein the detecting of the temperatures comprises:

generating a temperature detection enable signal to control a temperature detect operation for the memory cells in response to the synchronizing signal; and

detecting the temperatures of the memory cells in accordance with the temperature detection enable signal.

7. The method of claim 1, further comprising outputting the detected temperatures of the memory cells to the controller.

8. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells;

an operation control signal generator configured to receive a request for performing a target operation from a controller and to generate a synchronizing signal for performing the target operation; and

a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

9. The semiconductor memory device of claim 8, wherein the operation control signal generator generates an operation start pulse representing that the target operation starts and an operation end pulse representing that the target operation is completed.

10. The semiconductor memory device of claim 9, wherein the temperature detect circuit detects the temperatures of the plurality of memory cells in response to the operation end pulse.

11. The semiconductor memory device of claim 9, wherein, when the target operation is a program or erase operation, the operation control signal generator generates the operation start pulse in response to a write enable signal received from the controller.

12. The semiconductor memory device of claim 9, wherein, when the target operation is a read operation, the operation control signal generator generates the operation start pulse in response to a read enable signal received from the controller.

13. The semiconductor memory device of claim 9, wherein, when the target operation is a program or erase operation, the operation control signal generator generates the operation end pulse when a pass or a fail of the program or erase operation is determined.

14. The semiconductor memory device of claim 9, wherein, when the target operation is a read operation, the operation control signal generator generates the operation end pulse when fail of the read operation is determined or data is read in accordance with the read operation.

15. The semiconductor memory device of claim 9, wherein the operation control signal generator transmits the operation end pulse to the temperature detect circuit as the synchronizing signal.

16. The semiconductor memory device of claim 8, wherein the target operation includes at least one of a program related operation, a read related operation, and an erase related operation for the plurality of memory cells.

17. The semiconductor memory device of claim 8, wherein the temperature detect circuit comprises:

an enable circuit configured to generate a temperature detection enable signal configured to control a temperature detect operation for the memory cells in response to the synchronizing signal; and

a detect circuit configured to detect temperatures of the memory cells in accordance with the temperature detection enable signal.

18. The semiconductor memory device of claim 17, wherein the temperature detect circuit comprises an output circuit configured to output the detected temperatures of the memory cells to the controller.

19. The semiconductor memory device of claim 18, wherein the enable circuit comprises:

an inversion circuit configured to receive the synchronizing signal, invert the received synchronizing signal, and output an inverted synchronizing signal;

a selection output circuit configured to receive and perform a logic operation on the inverted synchronizing signal from the inversion circuit and an operation end pulse, and output a resultant signal; and

a flip flop configured to receive the resultant signal and output the temperature detection enable signal.

20. The semiconductor memory device of claim 19, wherein the selection output circuit performs an OR operation on the inverted synchronizing signal from the inversion circuit and the operation end pulse.