INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
First Claim
Patent Images
1. An integrated circuit (IC) device comprising:
- a plurality of word lines that extend on a substrate parallel to a main surface of the substrate and are separated from one another in a first direction perpendicular to the main surface;
a channel region that extends in a first region on the substrate through the plurality of word lines;
a bit line contact pad that is on the channel region and contacts an upper surface of the channel region;
a bit line that contacts the bit line contact pad in the first region and extends on the bit line contact pad in a second direction parallel to the main surface of the substrate;
a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height lower than that of the channel region; and
a common source via contact that contacts an upper surface of the common source line in the word line cut region and extends from the upper surface of the common source line in a direction away from the substrate.
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Abstract
An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.
30 Citations
35 Claims
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1. An integrated circuit (IC) device comprising:
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a plurality of word lines that extend on a substrate parallel to a main surface of the substrate and are separated from one another in a first direction perpendicular to the main surface; a channel region that extends in a first region on the substrate through the plurality of word lines; a bit line contact pad that is on the channel region and contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad in the first region and extends on the bit line contact pad in a second direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region and extends from the upper surface of the common source line in a direction away from the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9-15. -15. (canceled)
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16. An integrated circuit (IC) device comprising:
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a peripheral circuit on a substrate; a semiconductor layer on the peripheral circuit; a memory cell array region on the semiconductor layer and overlapping the peripheral circuit in a vertical direction, the memory cell array region comprising a plurality of memory cell arrays and a common source line tab region between adjacent two of the plurality of memory cell arrays; a plurality of word lines that extend on the semiconductor layer, parallel to a main surface of the substrate, and are included in each of the plurality of memory cell arrays and separated from one another in a first direction perpendicular to the main surface of the substrate; a plurality of channel regions that extend on the semiconductor layer in the first direction, passing through the plurality of word lines; a plurality of bit line contact pads that are on the plurality of channel regions to contact the plurality of channel regions; a plurality of bit lines that extend in a region separated from the common source line tab region, in a second direction parallel to the main surface of the substrate and contact a plurality of bit line contact pads; a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height lower than that of the plurality of channel regions; and at least one common source via contact that contacts an upper surface of the common source line in the common source line tab region and extends from the upper surface of the common source line in a direction away from the substrate. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24-31. -31. (canceled)
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32. An integrated circuit (IC) device comprising:
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at least one ground select line, a plurality of word lines, and at least one string select line sequentially stacked on a substrate, extending parallel to a main surface of the substrate and being spaced apart from one another with an insulating layer interposed between each separation in a first direction perpendicular to the main surface; a channel region extending in a first region on the substrate through the at least one ground select line, the plurality of word lines, and the at least one string select line; a dummy channel region extending in a second region separated from the first region on the substrate through the at least one ground select line, the plurality of word lines, and the at least one string select line; a bit line contact pad deposited on the channel region and contacting an upper surface of the channel region; a bit line contacting the bit line contact pad in the first region and extending on the bit line contact pad in a second direction parallel to the main surface of the substrate; a common source line partially filling a word line cut region, the word line cut region extending in a third direction on a side of the at least one ground select line, the plurality of word lines, and the at least one string select line, the third direction being parallel to the main surface of the substrate and intersecting the second direction; a word line cut region buried insulating layer deposited on the common source line in the word line cut region to fill up the word line cut region; a common source via contact surrounded by the word line cut region buried insulating layer, contacting an upper surface of the common source line in the word line cut region and extending from the upper surface of the common source line in a direction away from the substrate in the second region; a first upper wiring layer covering the bit line in the first region with an upper insulating layer interposed therebetween; and a second upper wiring layer formed at a level the same as that of the first upper wiring layer in the second region and being connected to the common source via contact. - View Dependent Claims (33, 34, 35)
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Specification