ARRAY SUBSTRATE AND DISPLAY PANEL
First Claim
1. An array substrate comprising a display region and a frame region surrounding the display region, wherein:
- the display region consists of a common electrode layer, a touch line layer, a gate electrode layer, and a plurality of second touch lines which are in parallel with the gate electrode lines, whereinthe common electrode layer comprises a plurality of common electrode units,the touch line layer comprises a plurality of first touch lines electrically connected to the common electrode units, andthe gate electrode layer comprises a plurality of gate electrode lines extending along a first direction, andeach of the common electrode units is electrically connected to one of the second touch lines through a via hole; and
the frame region consists of a plurality of first switches and a plurality of test lines extending along a second direction, wherein at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches.
1 Assignment
0 Petitions
Accused Products
Abstract
The present disclosure provides an array substrate including a display region and a frame region surrounding the display region. The display region further includes a plurality of second touch lines which are in parallel with the gate electrode lines, and each of the common electrode units is electrically connected to one of the second touch lines through a via hole. The frame region consists of a plurality of first switches and a plurality of test lines extending along a second direction, at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches.
-
Citations
20 Claims
-
1. An array substrate comprising a display region and a frame region surrounding the display region, wherein:
-
the display region consists of a common electrode layer, a touch line layer, a gate electrode layer, and a plurality of second touch lines which are in parallel with the gate electrode lines, wherein the common electrode layer comprises a plurality of common electrode units, the touch line layer comprises a plurality of first touch lines electrically connected to the common electrode units, and the gate electrode layer comprises a plurality of gate electrode lines extending along a first direction, and each of the common electrode units is electrically connected to one of the second touch lines through a via hole; and the frame region consists of a plurality of first switches and a plurality of test lines extending along a second direction, wherein at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification