Regulator Circuits and Methods

• US 20170229879A1
• Filed: 02/03/2017
• Published: 08/10/2017
• Est. Priority Date: 02/08/2016
• Status: Active Grant

• Current Assignee: Perceptia IP Pty., Ltd.
• Original Assignee: Perceptia Devices Australia Pty. Ltd.
• Inventors: Jenkins, Julian
• Granted Patent: US 10,320,218 B2
• Time in Patent Office: Days
• CPC Class Codes: H02J 7/00714 in response to battery charging or discharging current
• CPC Class Codes: H02J 7/007182 in response to battery voltage
• CPC Class Codes: H03M 1/001 Analogue/digital/analogue conversion

Abstract

A voltage or current regulator has a power DAC and ADC in a negative feedback loop, locked to a reference voltage or current. The ADC may have one or more parallel comparators followed by one or more parallel filters. The regulator may include a multiplexer to select between filter output signals and to forward the selected signal to the power DAC. The regulator may receive power management mode control codes to modify filter behavior and/or to select between multiple parallel filters. By modifying the loop behavior, the regulator is able to swiftly change between power management modes supporting different power level and noise profiles. Regulators with a single comparator can lock the output to a single reference voltage or current. Regulators with two comparators can regulate the output to vary within a range limited by an upper and a lower reference voltage or current.

Claims

1. A method of regulating supply energy in a digital regulator, comprising:

receiving a first digital control code;

receiving raw energy from a power supply;

using a power digital-to-analog convertor (DAC), forwarding a portion of the raw energy to a power load, wherein the portion is determined by the first digital control code;

sensing a physical quantity related to the portion of the raw energy in the power load, and forwarding the sensed physical quantity to an analog-to-digital converter (ADC);

receiving a first reference physical quantity and forwarding it to the ADC;

in the ADC, based on the first reference physical quantity and the sensed physical quantity, generating an updated first digital control code; and

regularly repeating the previous steps with the updated first digital control code to obtain a proportional relation between the sensed physical quantity and the first reference physical quantity.

2. The method of claim 1 wherein the sensed physical quantity includes at least one of a voltage and a current.

3. The method of claim 1 wherein the sensed physical quantity includes a quantity other than a voltage or a current.

4. The method of claim 1, further comprising filtering the digital control code.

5. The method of claim 4, wherein filtering includes using a pole at frequency zero.

6. The method of claim 4, wherein filtering includes using two poles at frequency zero and a single zero at a non-zero frequency.

7. The method of claim 1, wherein the ADC comprises a first clocked comparator and a first digital filter, further comprising:

receiving a clock signal;

in the first clocked comparator, at a time of receiving the clock signal, comparing the sensed physical quantity to the first reference physical quantity to obtain a first clocked comparator output signal;

forwarding the first clocked comparator output signal to the first digital filter; and

in the first digital filter, filtering the first clocked comparator output signal to obtain the updated first digital control code and to allow the sensed physical quantity to lock to the first reference physical quantity.

8. The method of claim 7, wherein the ADC comprises a second clocked comparator, further comprising:

receiving a second reference physical quantity;

forwarding the second reference physical quantity to the second clocked comparator;

in the second clocked comparator, at the time of receiving the clock signal, comparing the sensed physical quantity to the second reference physical quantity to obtain a second clocked comparator output signal;

combining the first and second clocked comparator output signals to obtain a combined filter input signal;

forwarding the combined filter input signal to the first digital filter; and

in the first digital filter, filtering the combined filter input signal to obtain the updated first digital control code and to allow the sensed physical quantity to vary between the first and second reference physical quantities.

9. The method of claim 8, wherein combining comprises:

receiving the first and second clocked comparator output signals;

producing a combined filter input signal “

1”

when the first clocked comparator output signal indicates that the sensed physical quantity has a value greater than the first reference physical quantity;

producing a combined filter input signal “

−

1”

when the second clocked comparator output signal indicates that the sensed physical quantity has a value less than the second reference physical quantity;

producing a combined filter input signal “

0”

when the first and second clocked comparator output signals indicate that the sensed physical quantity has a value in between the first and second reference physical quantities.

10. The method of claim 7, further comprising:

receiving a mode control code;

forwarding the mode control code to the first digital filter; and

in the first digital filter, modifying filter behavior based on the mode control code.

11. The method of claim 7, wherein the ADC comprises a second digital filter and a digital multiplexer, further comprising:

receiving a mode control code;

forwarding the first clocked comparator output signal to the second digital filter;

in the second digital filter, filtering the first clocked comparator output signal to obtain a second updated digital control code; and

in the digital multiplexer, based on the mode control code, selecting one of the first and the second updated digital control codes to determine the portion of raw energy.

12. The method of claim 11, further comprising:

forwarding the mode control code to at least one of the first and the second digital filters; and

in the at least one of the first and the second digital filters, modifying filter behavior based on the mode control code.

13. A method of regulating supply energy in an analog regulator, comprising:

receiving raw energy from a power supply;

receiving an analog control signal;

from a power stage, forwarding a portion of the raw energy to a power load, wherein the portion is determined by the analog control signal;

sensing a physical quantity related to the portion of the raw energy in the power load, and forwarding the sensed physical quantity to a comparator;

receiving and forwarding a reference physical quantity to the comparator;

receiving a clock signal;

in the comparator, comparing the sensed physical quantity to the reference physical quantity to obtain a comparator output signal;

forwarding the comparator output signal to two or more analog filters;

in the two or more analog filters, filtering the comparator output signal to obtain two or more updated analog control signals;

forwarding the two or more updated analog control signals to an analog multiplexer;

receiving a mode control code;

in the analog multiplexer, based on the mode control code, selecting one of the two or more updated analog control signals to determine the portion of raw energy; and

continuously repeating the previous steps with the selected one of the two or more updated analog control signals to obtain a proportional relation between the sensed physical quantity and the first reference physical quantity.

14. The method of claim 13 wherein the sensed physical quantity includes a voltage.

15. The method of claim 13 wherein the sensed physical quantity includes a current.

16. A level regulator circuit, comprising:

a power digital-to-analog converter (DAC) with a raw energy input, a digital control code input, and a regulated power output, wherein the raw energy input is configured to receive raw energy from a power supply, and the regulated power output is configured to deliver regulated energy to a power load;

an analog-to-digital converter (ADC), with a first input coupled with the regulated power output, and with a second input configured to receive a reference physical quantity; and

a first digital filter, with;

an input coupled to an ADC output;

a mode control code input, wherein the digital filter is capable of modifying filter behavior based on a code received on the mode control code input; and

an output at least part of the time directly or indirectly coupled with the power DAC digital control code input.

17. The level regulator circuit of claim 16, further comprising:

a second digital filter, with

an input coupled with the ADC output; and

a mode control code input, wherein the second digital filter is capable of modifying filter behavior based on the code received on the mode control code input;

an output; and

a digital multiplexer with inputs coupled with the first and second digital filter outputs, wherein the digital multiplexer is configured to receive a mode control code, and based on the mode control code select one of the first and second digital filters, and with an output coupled with the power DAC.

18. A range regulator circuit, comprising:

a power digital-to-analog converter (DAC) with a raw energy input, a digital control code input, and a regulated power output, wherein the raw energy input is configured to receive raw energy from a power supply, and the regulated power output is configured to deliver regulated energy to a power load;

a first and a second clocked comparator, each with a first input coupled with the regulated power output, and with a second input configured to each receive a separate reference physical quantity; and

a first digital filter, with inputs coupled with outputs of the first and second clocked comparator, and with an output coupled with the power DAC digital control code input.

19. The range regulator circuit of claim 18, further comprising:

one or more additional digital filters, each with inputs coupled with outputs of the first and second clocked comparator; and

a digital multiplexer with inputs each coupled with a separate output of the first and the one or more additional digital filters, wherein the digital multiplexer is configured to receive a mode control code, and based on the mode control code select one of the first and the one or more additional digital filters, and with an output coupled with the power DAC.

20. The range regulator circuit of claim 18, wherein the first digital filter has a mode control code input, wherein the first digital filter is capable of modifying filter behavior based on a code received on the mode control code input.

21. The range regulator circuit of claim 18, wherein the first digital filter is configured to keep a physical quantity sensed at the regulated power output between the two reference physical quantities.

23. The two-step regulator system of claim 21, wherein the energy storage device includes at least one of a capacitor, an inductor, and a rechargeable battery.

24. The two-step regulator system of claim 21, wherein the range regulator is configured to draw a constant current from the power supply and the level regulator is configured to deliver a constant voltage to the power load.

22. A two-step regulator system, comprising:

a range regulator with a raw energy input configured to receive raw energy from a power supply, two reference inputs, and a regulated power output coupled to an energy storage device;

a level regulator with a raw energy input coupled to the range regulator regulated power output, one reference input, and a regulated power output coupled to a power load;

wherein;

the range regulator is configured to regulate a first physical quantity on the energy storage device between limits determined by signal levels on the two range regulator reference inputs; and

the level regulator is configured to regulate a second physical quantity on the power load to a level determined by a signal level on the level regulator reference input.