MEMORY REFRESH OPERATION WITH PAGE OPEN

• US 20170236575A1
• Filed: 05/03/2017
• Published: 08/17/2017
• Est. Priority Date: 12/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: BAINS, Kuljit, QUERBACH, Bruce, HALBERT, John
• Granted Patent: US 9,824,743 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Claims

1. A system comprising:

one or more processors;

a memory device;

a memory controller communicatively coupled to the one or more processors; and

an interface to communicatively couple the memory controller and the memory device;

wherein the memory device includes;

a memory array including a plurality of memory banks; and

a control logic to provide control operations for the memory device including a page open refresh mode;

wherein the control logic is to perform a refresh cycle in response to a refresh command from the memory controller with a memory page of the memory array being open, the refresh operation including;

precharge of one or more memory banks of the plurality of memory banks,

refresh of the one or more memory banks, and

activation of the memory page.

2. The system of claim 1, wherein the memory device includes a mode register set including a mode register to store an indication to enable or disable the page open refresh mode.

3. The system of claim 2, wherein the mode register for page open refresh mode is set in response to a received write command.

4. The system of claim 1, wherein the refresh command is one of a refresh command for all memory banks of the memory device or a refresh command for a specific memory bank of the memory device.

5. The system of claim 1, wherein the control logic of the memory device is operable to perform the refresh cycle without receipt of a precharge command or an activate command from the memory controller using the interface.

6. The system of claim 1, further comprising one or more of:

a display communicatively coupled to the one or more processors;

a network interface communicatively coupled to the one or more processors;

or

a battery coupled to the one or more processors.

7. A method comprising:

receiving a refresh command at a memory device, wherein a memory page is open at a time of receipt of the refresh command; and

performing a page open refresh by the memory device, the performance of the page open refresh including;

providing an internal precharge command for the memory device,

precharging one of more memory banks of the memory device,

providing an internal refresh command for the memory device,

performing a refresh cycle for the one or more memory banks of the memory device,

providing an internal activate command for the memory device, and

reopening the one or more banks of the memory device.

8. The method of claim 7, further comprising reading a mode register for a page open refresh mode, the performance of the page open refresh being dependent on the mode register being enabled.

9. The method of claim 8, further comprising enabling or disabling the mode register in response to a received write command.

10. The method of claim 7, wherein the refresh command is one of a refresh command for all memory banks of the memory device or a refresh command for a specific memory bank of the memory device.

11. The method of claim 7, wherein the page open refresh is performed without receipt of a precharge command or an activate command by the memory device.

12. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processing units, cause the one or more processing units to perform operations comprising:

receiving a refresh command at a memory device, wherein a memory page is open at a time of receipt of the refresh command; and

performing a page open refresh by the memory device, the performance of the page open refresh including;

providing an internal precharge command for the memory device,

precharging one of more memory banks of the memory device,

providing an internal refresh command for the memory device,

performing a refresh cycle for the one or more memory banks of the memory device,

providing an internal activate command for the memory device, and

reopening the one or more banks of the memory device.

13. The medium of claim 12, further comprising instructions that, when executed by the one or more processing units, cause the one or more processing units to perform operations comprising:

reading a mode register for a page open refresh mode, the performance of the page open refresh being dependent on the mode register being enabled.

14. The medium of claim 13, further comprising instructions that, when executed by the one or more processing units, cause the one or more processing units to perform operations comprising:

enabling or disabling the mode register in response to a received write command.

15. The medium of claim 12, wherein the refresh command is one of a refresh command for all memory banks of the memory device or a refresh command for a specific memory bank of the memory device.

16. The medium of claim 12, wherein the page open refresh is performed without receipt of a precharge command or an activate command by the memory device.

17. An apparatus comprising:

means for receiving a refresh command at a memory device, wherein a memory page is open at a time of receipt of the refresh command; and

means for performing a page open refresh by the memory device, the means for performance of the page open refresh including;

means for providing an internal precharge command for the memory device,

means for precharging one of more memory banks of the memory device,

means for providing an internal refresh command for the memory device,

means for performing a refresh cycle for the one or more memory banks of the memory device,

means for providing an internal activate command for the memory device, and

means for reopening the one or more banks of the memory device.

18. The apparatus of claim 17, further comprising:

means for reading a mode register for a page open refresh mode, the performance of the page open refresh being dependent on the mode register being enabled.

19. The apparatus of claim 18, further comprising:

means for enabling or disabling the mode register in response to a received write command.

20. The apparatus of claim 17, wherein the refresh command is one of a refresh command for all memory banks of the memory device or a refresh command for a specific memory bank of the memory device.

21. The apparatus of claim 17, wherein the page open refresh is performed without receipt of a precharge command or an activate command by the memory device.