SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

• US 20170263535A1
• Filed: 01/27/2017
• Published: 09/14/2017
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: NAKANO, Hayato, NAKAMURA, Hideyo
• Granted Patent: US 10,170,395 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/01 Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H05K 1/0213 Electrical arrangements not otherwise provided for

Abstract

A semiconductor device including a semiconductor module 10A, a semiconductor module 10B that has a lower switching voltage threshold than the semiconductor module 10A, and busbars 331 and 32 that connect the semiconductor module 10A and the semiconductor module 10B in parallel to a common terminal. The semiconductor module 10B is connected at a connection point on the busbar 32 at which the inductance relative to the common terminal is higher than that of the semiconductor module 10A. The semiconductor module 10B with the low threshold voltage is turned ON faster than the semiconductor module 10A with the high threshold voltage for input of a common switching voltage, but can restrict the rising of the current due to the high inductance of the busbar 32, thereby enabling restriction of the current imbalance.

Claims

1. A semiconductor device comprising:

a first semiconductor module;

a second semiconductor module housing a second semiconductor element that has a switching voltage threshold that is lower than a switching voltage threshold of a first semiconductor element of the first semiconductor module; and

a busbar that connects respective external terminals of the first semiconductor module and the second semiconductor module in parallel to a common terminal, wherein

the second semiconductor module is connected to a connection point on the busbar at which an inductance of a current path to the common terminal is greater than an inductance of a current path from a connection point of the first semiconductor module to the common terminal.

2. The semiconductor device according to claim 1, wherein

the second semiconductor module is connected to a connection point at which a total of an inductance between the connection point of the second semiconductor module and the common terminal on the busbar and an inductance of a current path to the second semiconductor element in the second semiconductor module is greater than a total of an inductance between the connection point of the first semiconductor module and the common terminal on the busbar and an inductance of a current path to the first semiconductor element in the first semiconductor module.

3. The semiconductor device according to claim 1, wherein

the first semiconductor module includes a plurality of the first semiconductor elements connected in parallel at a connection point on the busbar,

the second semiconductor module includes a plurality of second semiconductor elements connected in parallel at a connection point on the busbar, and

the switching voltage thresholds of the plurality of the second semiconductor elements is lower than the switching voltage thresholds of the plurality of the first semiconductor elements in an average value or a largest value.

4. The semiconductor device according to claim 1, wherein

a difference between the switching voltage threshold of the first semiconductor element housed in the first semiconductor module and the switching voltage threshold of the second semiconductor element housed in the second semiconductor module is determined according to a difference between inductances of current paths from the common terminal of the busbar to the connection points of the respective semiconductor modules.

5. The semiconductor device according to claim 4, wherein

when the difference between the switching voltage threshold of the first semiconductor element housed in the first semiconductor module and the switching voltage threshold of the second semiconductor element housed in the second semiconductor module is 1.8 V, the difference between inductances of current paths from the common terminal of the busbar to the connection points of the respective semiconductor modules is 10 nH.

6. The semiconductor device according to claim 1, further comprising:

another busbar connected to another common terminal in parallel with another external terminal of each of the first semiconductor module and the second semiconductor module, wherein

the busbar and the another busbar are arranged such that portions thereof in which current flows in opposite directions are opposite each other.

7. A method of manufacturing the semiconductor device according to claim 1, comprising:

measuring the switching voltage threshold of each semiconductor element housed in a plurality of the semiconductor modules;

selecting a first semiconductor element housed in the first semiconductor module from among the plurality of semiconductor elements and selecting a second semiconductor element with a lower switching voltage threshold than the first semiconductor element housed in the first semiconductor module to be housed in the second semiconductor module;

connecting the first semiconductor module to a connection point on the busbar; and

connecting the second semiconductor module to a connection point on the busbar at which an inductance relative to the common terminal is higher than that of the first semiconductor module.

8. The semiconductor device manufacturing method according to claim 7, further comprising:

assembling the first semiconductor module and the second semiconductor module;

measuring inductances from the common terminal of the busbar to the connection points of the respective semiconductor modules; and

determining a difference that can be allowed between the switching voltage thresholds of the semiconductor elements, according to a difference between the inductances from the common terminal of the busbar to the connection points of the respective semiconductor modules.

9. A semiconductor device comprising:

a first semiconductor module and a second semiconductor module that each include a first semiconductor element connected between a first external terminal and a second external terminal and a second semiconductor element connected between the second external terminal and a third external terminal;

a first busbar that connects the first external terminal of the first semiconductor module and the first external terminal of the second semiconductor module in parallel to a first common terminal;

a second busbar that connects the second external terminal of the first semiconductor module and the second external terminal of the second semiconductor module in parallel to a second common terminal; and

a third busbar that connects the third external terminal of the first semiconductor module and the third external terminal of the second semiconductor module in parallel to a third common terminal, wherein

the first semiconductor element of the first semiconductor module has a higher switching voltage threshold than the first semiconductor element of the second semiconductor module,

the second semiconductor element of the first semiconductor module has a lower switching voltage threshold than the second semiconductor element of the second semiconductor module,

an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is lower than an inductance of a current path from the first common terminal to the first semiconductor element in the second semiconductor module, and

an inductance of a current path from the third common terminal to the second semiconductor element of the first semiconductor module is higher than an inductance of a current path from the third common terminal to the second semiconductor element of the second semiconductor module.

10. The semiconductor device according to claim 9, wherein

a difference between the switching voltage threshold of the first semiconductor element housed in the first semiconductor module and the switching voltage threshold of the first semiconductor element housed in the second semiconductor module is determined according to a difference between inductances of current paths from the first common terminal to the respective first semiconductor elements, and

a difference between the switching voltage threshold of the second semiconductor element housed in the first semiconductor module and the switching voltage threshold of the second semiconductor element housed in the second semiconductor module is determined according to a difference between inductances of current paths from the third common terminal to the respective second semiconductor elements.

11. The semiconductor device according to claim 10, wherein

when the difference between the switching voltage threshold of the first semiconductor element housed in the first semiconductor module and the switching voltage threshold of the first semiconductor element housed in the second semiconductor module is 1.8 V, the difference between inductances of current paths from the first common terminal to the respective first semiconductor elements is 10 nH, and

when the difference between the switching voltage threshold of the second semiconductor element housed in the first semiconductor module and the switching voltage threshold of the second semiconductor element housed in the second semiconductor module is 1.8 V, the difference between inductances of current paths from the third common terminal to the respective second semiconductor elements is 10 nH.

12. The semiconductor device according to claim 9, wherein

the first busbar and the third busbar are arranged such that portions thereof in which current flows in opposite directions are opposite each other.

13. The semiconductor device according to claim 9, wherein

the first semiconductor module and the second semiconductor module each include a plurality of the first semiconductor elements and the second semiconductor elements,

the plurality of first semiconductor elements of the first semiconductor module has a higher switching voltage threshold than the plurality of first semiconductor elements of the second semiconductor module, and

the plurality of second semiconductor elements of the first semiconductor module has a lower switching voltage threshold than the plurality of second semiconductor elements of the second semiconductor module.

14. A method of manufacturing the semiconductor device according to claim 9, comprising:

measuring the switching voltage threshold of each semiconductor element housed in a plurality of the semiconductor modules;

selecting, from among the plurality of semiconductor elements, a first semiconductor element housed in the first semiconductor module and a second semiconductor element housed in the first semiconductor module, a first semiconductor element with a lower switching voltage threshold than the first semiconductor element housed in the first semiconductor module to be housed in the second semiconductor module, and a second semiconductor element with a higher switching voltage threshold than the second semiconductor element housed in the first semiconductor module to be housed in the second semiconductor module;

connecting the first external terminal of the first semiconductor module to the first busbar and connecting the third external terminal of the first semiconductor module to the third busbar; and

connecting the first external terminal of the second semiconductor module to the first busbar and connecting the third external terminal of the second semiconductor module to the third busbar, wherein

an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is made lower than an inductance of a current path to the second semiconductor element in the second semiconductor module, and

an inductance of a current path from the third common terminal to the second semiconductor element of the first semiconductor module is made higher than an inductance of a current path from the third common terminal to the second semiconductor element of the second semiconductor module.

15. The semiconductor device manufacturing method according to claim 14, further comprising:

assembling the first semiconductor module and the second semiconductor module;

measuring inductances from the common terminals of the first busbar and the third busbar to the connection points of the respective semiconductor modules;

determining a difference between the switching voltage thresholds of the first semiconductor element and the second semiconductor element housed in the respective semiconductor modules, according to a difference between the inductances from the common terminal of the first busbar to the connection points of the respective semiconductor modules; and

determining a difference between the inductances from the common terminal of the third busbar to the connection points of the respective semiconductor modules and a difference between the switching voltage thresholds of the first semiconductor element and the second semiconductor element housed in the respective semiconductor modules.

16. A semiconductor device comprising:

a first semiconductor module and a second semiconductor module that each include a first semiconductor device connected between a first external terminal and a second external terminal and a second semiconductor device connected between the second external terminal and a third external terminal;

a first busbar that connects the first external terminal of the first semiconductor module and the first external terminal of the second semiconductor module in parallel to a first common terminal;

a second busbar that connects the third external terminal of the first semiconductor module and the third external terminal of the second semiconductor module in parallel to a second common terminal, wherein

the first semiconductor device of the first semiconductor module has a higher switching voltage threshold than the first semiconductor device of the second semiconductor module,

the second semiconductor device of the first semiconductor module has a lower switching voltage threshold than the second semiconductor device of the second semiconductor module, and

an inductance of a current path from the first common terminal to the second common terminal through the first semiconductor device in the first semiconductor module and the second semiconductor device in the second semiconductor module is lower than an inductance of a current path from the first common terminal to the second common terminal through the first semiconductor device in the second semiconductor module and the second semiconductor device in the first semiconductor module.

17. A method of manufacturing the semiconductor device according to claim 16, comprising:

measuring the switching voltage threshold of the first semiconductor device and the second semiconductor device included in each of a plurality of the semiconductor modules;

selecting, from among the plurality of semiconductor modules, a first semiconductor module and selecting a second semiconductor module in which the first semiconductor device has a lower switching voltage threshold than the first semiconductor module and the second semiconductor device has a higher switching voltage threshold than the first semiconductor module;

connecting the first external terminal of the first semiconductor module to the first busbar and connecting the third external terminal of the first semiconductor module to the second busbar; and

connecting the first external terminal of the second semiconductor module to the first busbar and connecting the third external terminal of the second semiconductor module to the second busbar, wherein

an inductance of a current path from the first common terminal to the second common terminal through the first semiconductor device in the first semiconductor module and the second semiconductor device in the second semiconductor module is made lower than an inductance of a current path from the first common terminal to the second common terminal through the first semiconductor device in the second semiconductor module and the second semiconductor device in the first semiconductor module.